# US 2025/0095699 A1 · Programmable column access > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2025/0095699 A1 - Document ID: US20250095699A1 - Status: Published application - Kind: A1 - Application number: 18/962,783 - Filed: 2024-11-27 - Published: 2025-03-20 - Earliest claimed: 2021-06-17 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Hyunyoo Lee; Kang-Yong Kim; Taeksang Song - Web page: https://patentgrep.com/patent/US20250095699A1 ## CPC - G11C 7/1039: {using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers} - G11C 11/4087: {Address decoders, e.g. bit - or word line decoders; Multiple line decoders} - G11C 7/08: Control thereof - G11C 7/1012: {Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating} - G11C 7/1063: {Control signal output circuits, e.g. status or busy flags, feedback command signals} - G11C 7/109: {Control signal input circuits} - G11C 8/06: Address interface arrangements, e.g. address buffers - G11C 8/10: Decoders - G11C 11/005: {comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells} - G11C 11/2253: {Address circuits or decoders} - G11C 11/2255: {Bit-line or column circuits} - G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits - G11C 11/4091: Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating - G11C 11/221: {using ferroelectric capacitors} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Methods, systems, and devices for programmable column access are described. A device may transfer voltages from memory cells of a row in a memory array to respective digit lines for the memory cells. The voltages may be indicative of logic values stored at the memory cells. The device may communicate respective control signals to a set of multiplexers coupled with the digit lines, where each multiplexer is coupled with a respective subset of the digit lines. Each multiplexer may couple a digit line of the respective subset of digit lines with a respective sense component for that multiplexer based on the respective control signal for that multiplexer. ## Claims ### Claim 1 A memory device, comprising: a memory array comprising a row of memory cells coupled with a set of multiplexers; and one or more controllers coupled with the memory array and the set of multiplexers, the one or more controllers operable to cause the memory device to: activate a word line for the row of memory cells based on receiving at least one activation command; transfer respective voltages stored at the memory cells of the row to digit lines for the memory cells based on activating the word line, the respective voltages indicative of logic values stored at the memory cells; communicate a respective control signal to each multiplexer of a set of multiplexers coupled with the digit lines, wherein each multiplexer is coupled with a subset of noncontiguous digit lines; and sense a plurality of logic values from memory cells coupled with a respective plurality of noncontiguous digit lines based on communicating the respective control signals. ### Claim 2 (depends on 1) The memory device of claim 1, wherein, to sense the plurality of logic values, the one or more controllers are further configured to cause the memory device to: couple a first digit line from each subset of noncontiguous digit lines with a respective sense component of a set of sense components based on a respective control signal; sense a voltage from each first digit line based on coupling the first digit line with the respective sense component, the voltage indicative of a logic value stored at a memory cell associated with the first digit line; and latch the voltage from each first digit line. ### Claim 3 (depends on 1) The memory device of claim 1, wherein the at least one activation command is received consecutively, and the one or more controllers are further configured to cause the memory device to: receiving, after receiving the at least one activation command, at least one read command indicating address information, wherein transferring the respective voltages is based on the address information. ### Claim 4 (depends on 3) The memory device of claim 3, wherein the one or more controllers are further configured to cause the memory device to: communicate, over a data bus, the plurality of logic values based on receiving the at least one read command, wherein each logic value of the plurality of logic values is associated with a respective digit line of the plurality of noncontiguous digit lines. ### Claim 5 (depends on 3) The memory device of claim 3, wherein the address information comprises a plurality of non-sequential column addresses associated with memory cells of the plurality of noncontiguous digit lines. ### Claim 6 (depends on 1) The memory device of claim 1, wherein, to communicate the respective control signals, the one or more controllers are further configured to cause the memory device to: communicate a first control signal to a first multiplexer of the set of multiplexers, the first control signal having a first value; and communicate a second control signal to a second multiplexer of the set of multiplexers, the second control signal having a second value different than the first value. ### Claim 7 (depends on 6) The memory device of claim 6, wherein, to communicate the respective control signals, the one or more controllers are further configured to cause the memory device to: communicate a third control signal to a third multiplexer of the set of multiplexers, the third control signal having a third value different than at least one of the first value or the second value. ### Claim 8 (depends on 1) The memory device of claim 1, wherein the at least one activation command indicates address information for the memory cells, and wherein values for each control signal are based on the address information. ### Claim 9 A method by a memory device, comprising: activating a word line for a row of memory cells of a memory array based on receiving at least one activation command; transferring respective voltages stored at the memory cells of the row to digit lines for the memory cells based on activating the word line, the respective voltages indicative of logic values stored at the memory cells; communicating a respective control signal to each multiplexer of a set of multiplexers coupled with the digit lines, wherein each multiplexer is coupled with a subset of noncontiguous digit lines; and sense a plurality of logic values from memory cells coupled with a respective plurality of noncontiguous digit lines based on communicating the respective control signals. ### Claim 10 (depends on 9) The method of claim 9, wherein sensing the plurality of logic values further comprises: coupling a first digit line from each subset of noncontiguous digit lines with a respective sense component of a set of sense components based on a respective control signal; sensing a voltage from each first digit line based on coupling the first digit lines with the respective sense component, the voltage indicative of a logic value stored at a memory cell associated with the first digit line; and latching the voltage from each first digit line. ### Claim 11 (depends on 9) The method of claim 9, wherein the at least one activation command is received consecutively, the method further comprising: receiving, after receiving the at least one activation command, at least one read command indicating address information, wherein transferring the respective voltages is based on the address information. ### Claim 12 (depends on 11) The method of claim 11, further comprising: communicating, over a data bus, the plurality of logic values based on receiving the at least one read command, wherein each logic value of the plurality of logic values is associated with a respective digit line of the plurality of noncontiguous digit lines. ### Claim 13 (depends on 11) The method of claim 11, wherein the address information comprises a plurality of non-sequential column addresses associated with memory cells of the plurality of noncontiguous digit lines. ### Claim 14 (depends on 9) The method of claim 9, wherein communicating the respective control signals further comprises: communicating a first control signal to a first multiplexer of the set of multiplexers, the first control signal having a first value; and communicating a second control signal to a second multiplexer of the set of multiplexers, the second control signal having a second value different than the first value. ### Claim 15 (depends on 14) The method of claim 14, wherein communicating the respective control signals further comprises: communicating a third control signal to a third multiplexer of the set of multiplexers, the third control signal having a third value different than at least one of the first value or the second value. ### Claim 16 (depends on 9) The method of claim 9, wherein the at least one activation command indicates address information for the memory cells, and wherein values for each control signal are based on the address information. ### Claim 17 A non-transitory computer-readable medium storing processor-executable code, the code comprising instructions executable by one or more processors to: activate a word line for a row of memory cells of a memory array based on receiving at least one activation command; transfer respective voltages stored at the memory cells of the row to digit lines for the memory cells based on activating the word line, the respective voltages indicative of logic values stored at the memory cells; communicate a respective control signal to each multiplexer of a set of multiplexers coupled with the digit lines, wherein each multiplexer is coupled with a subset of noncontiguous digit lines; and sense a plurality of logic values from memory cells coupled with a respective plurality of noncontiguous digit lines based on communicating the respective control signals. ### Claim 18 (depends on 17) The non-transitory computer-readable medium of claim 17, wherein the instructions to sense the plurality of logic values are further executable by the one or more processors to: couple a first digit line from each subset of noncontiguous digit lines with a respective sense component of a set of sense components based on a respective control signal; sense a voltage from each first digit line based on coupling the first digit lines with the respective sense component, the voltage indicative of a logic value stored at a memory cell associated with the first digit line; and latch the voltage from each first digit line. ### Claim 19 (depends on 17) The non-transitory computer-readable medium of claim 17, wherein the at least one activation command is received consecutively, and the instructions are further executable by the one or more processors to: receiving, after receiving the at least one activation command, at least one read command indicating address information, wherein transferring the respective voltages is based on the address information. ### Claim 20 (depends on 19) The non-transitory computer-readable medium of claim 19, wherein the instructions are further executable by the one or more processors to: communicate, over a data bus, the plurality of logic values based on receiving the at least one read command, wherein each logic value of the plurality of logic values is associated with a respective digit line of the plurality of noncontiguous digit lines.