# US 2025/0095697 A1 · Bank to bank data transfer

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- Number: US 2025/0095697 A1
- Document ID: US20250095697A1
- Status: Published application
- Kind: A1
- Application number: 18/959,128
- Filed: 2024-11-25
- Published: 2025-03-20
- Earliest claimed: 2017-05-15
- Assignees: Lodestar Licensing Group LLC
- Applicants: Lodestar Licensing Group LLC
- Inventors: Perry L. Lea; Troy A. Manning
- Web page: https://patentgrep.com/patent/US20250095697A1

## CPC

- G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor}
- G06F 13/124: {where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine}
- G11C 7/1048: {Data bus control circuits, e.g. precharging, presetting, equalising}
- G11C 8/12: Group selection circuits, e.g. for memory block selection, chip selection, array selection
- G11C 11/408: Address circuits
- G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
- H03K 19/1733: {Controllable logic circuits (H03K19/177 takes precedence)}
- G11C 2207/002: Isolation gates, i.e. gates coupling bit lines to the sense amplifier
- G11C 2207/005: Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines
- G11C 2207/2236: Copy
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

The present disclosure includes apparatuses and methods for bank to bank data transfer. An example apparatus includes a plurality of banks of memory cells, an internal bus configured to transfer data between the plurality of banks and an external bus interface, and a bank-to-bank transfer bus configured to transfer data between the plurality of banks.

## Claims

### Claim 1

A method, comprising:
determining a direction to transfer data from a first memory bank of a plurality of memory banks to a second memory bank of the plurality of memory banks based on a command associated with bank-to-bank transfer; and
transferring the data from the first memory bank to the second memory bank via a bank-to-bank transfer bus according to the direction to transfer data from the first memory bank of the plurality of memory banks to the second memory bank of the plurality of memory banks.

### Claim 2 (depends on 1)

The method of claim 1, wherein transferring the data comprises:
transferring the data from the bank-to-bank transfer bus to the second memory bank via at least one shared input/output (SIO) line.

### Claim 3 (depends on 1)

The method of claim 1, further comprising:
coupling respective memory banks of the plurality of memory banks to the bank-to-bank transfer bus and to logic comprising a plurality of latches via a plurality of shared input/output lines, wherein transferring the data comprises:
transferring the data from the plurality of latches to the second memory bank via at least one of the plurality of shared input/output lines.

### Claim 4 (depends on 1)

The method of claim 1, further comprising:
configuring the bank-to-bank transfer bus to transfer the data from the first memory bank to the second memory bank based on a location of the first memory bank with respect to the bank-to-bank transfer bus and the second memory bank.

### Claim 5 (depends on 1)

The method of claim 1, wherein transferring the data comprises:
transferring the data from the first memory bank to the second memory bank via the bank-to-bank transfer bus according to the direction in response to a user input.

### Claim 6 (depends on 1)

The method of claim 1, further comprising:
determining a second direction to transfer data from the first memory bank of the plurality of memory banks to a third memory bank of the plurality of memory banks based on a second command associated with bank-to-bank transfer, the second direction different than the direction; and
transferring the data from the first memory bank to the third memory bank via the bank-to-bank transfer bus according to the second direction.

### Claim 7 (depends on 1)

The method of claim 1, wherein the data comprises a bit that indicates the direction.

### Claim 8

A memory apparatus, comprising:
a bank-to-bank transfer bus; and
a controller configured to:
determine a direction to transfer data from a first memory bank of a plurality of memory banks to a second memory bank of the plurality of memory banks based on a command associated with bank-to-bank transfer; and
transfer the data from the first memory bank to the second memory bank via the bank-to-bank transfer bus according to the direction to transfer data from the first memory bank of the plurality of memory banks to the second memory bank of the plurality of memory banks.

### Claim 9 (depends on 8)

The memory apparatus of claim 8, wherein the bank-to-bank transfer bus comprises a ring architecture.

### Claim 10 (depends on 8)

The memory apparatus of claim 8, further comprising:
a plurality of shared input/output lines coupling respective memory banks of the plurality of memory banks to the bank-to-bank transfer bus, wherein, to transfer the data, the controller is configured to:
transfer the data from the bank-to-bank transfer bus to the second memory bank via at least one SIO line of the plurality of shared input/output lines.

### Claim 11 (depends on 8)

The memory apparatus of claim 8, further comprising:
a plurality of shared input/output lines coupling respective memory bank of the plurality of memory banks to the bank-to-bank transfer bus; and
a plurality of latches coupled with the plurality of memory banks, wherein, to transfer the data, the controller is configured to:
transfer the data from the plurality of latches to the second memory bank via at least one of the plurality of shared input/output lines.

### Claim 12 (depends on 8)

The memory apparatus of claim 8, wherein the controller is further configured to:
reconfigure the bank-to-bank transfer bus to transfer the data from the first memory bank to the second memory bank based on a location of the first memory bank with respect to the bank-to-bank transfer bus and the second memory bank.

### Claim 13 (depends on 8)

The memory apparatus of claim 8, wherein the controller is further configured to:
receive a user input, wherein, to transfer the data, the controller is configured to:
transfer the data from the first memory bank to the second memory bank via the bank-to-bank transfer bus according to the direction in response to the user input.

### Claim 14 (depends on 8)

The memory apparatus of claim 8, wherein the controller is further configured to:
determine a second direction to transfer data from the first memory bank of the plurality of memory banks to a third memory bank of the plurality of memory banks based on a second command associated with bank-to-bank transfer, the second direction different than the direction; and
transfer the data from the first memory bank to the third memory bank via the bank-to-bank transfer bus according to the second direction.

### Claim 15 (depends on 8)

The memory apparatus of claim 8, wherein the data comprises a bit that indicates the direction.