# US 2025/0095694 A1 · Memory device and method of manufacturing the same

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- Number: US 2025/0095694 A1
- Document ID: US20250095694A1
- Status: Published application
- Kind: A1
- Application number: 18/952,621
- Filed: 2024-11-19
- Published: 2025-03-20
- Earliest claimed: 2021-07-30
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Jin Ha KIM
- Web page: https://patentgrep.com/patent/US20250095694A1

## CPC

- G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- H10B 43/10: characterised by the top-view layout
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A memory device, and a method of manufacturing the same, includes interlayer insulation layers spaced apart from each other and stacked, gate lines formed between the interlayer insulation layers, and a plug vertically passing through the interlayer insulation layers and the gate lines. Each of the gate lines includes a barrier layer formed along an inner wall of the interlayer insulation layer and the plug, a first conductive layer surrounded by the barrier layer, and a second conductive layer surrounded by the first conductive layer and having a grain size different from a grain size of the first conductive layer. A volume of the second conductive layer is variable along a direction in which the gate lines extend.

## Claims

### Claim 1

A memory device comprising:
interlayer insulation layers spaced apart from each other and stacked;
gate lines formed between the interlayer insulation layers; and
a plug vertically passing through the interlayer insulation layers and the gate lines,
wherein each of the gate lines comprises:
a barrier layer formed along an inner wall of the interlayer insulation layer and the plug;
a first conductive layer surrounded by the barrier layer; and
a second conductive layer surrounded by the first conductive layer and having a grain size different from a grain size of the first conductive layer,
wherein a volume of the second conductive layer is variable along a direction in which the gate lines extend.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the barrier layer comprises titanium nitride (TiN).

### Claim 3 (depends on 1)

The memory device of claim 1, wherein the first conductive layer and the second conductive layer are formed of materials having different melting points.

### Claim 4 (depends on 3)

The memory device of claim 3, wherein the material of the second conductive layer has a melting point lower than the material of the first conductive layer.

### Claim 5 (depends on 3)

The memory device of claim 3, wherein the first conductive layer is formed of a material having a melting point lower than a melting point of a material of the second conductive layer.

### Claim 6 (depends on 1)

The memory device of claim 1, wherein the grain size of the second conductive layer is less than the grain size of the first conductive layer.

### Claim 7 (depends on 1)

The memory device of claim 1, wherein the grain size of the first conductive layer is less than the grain size of the second conductive layer.

### Claim 8 (depends on 1)

The memory device of claim 1, wherein the first conductive layer is formed of tungsten (W), and the second conductive layer is formed of molybdenum (Mo).

### Claim 9 (depends on 1)

The memory device of claim 1, wherein the first conductive layer is formed of molybdenum (Mo), and the second conductive layer is formed of tungsten (W).

### Claim 10 (depends on 1)

The memory device of claim 1, wherein a portion of the plug protrudes above the interlayer insulation layers and the gate lines.

### Claim 11 (depends on 10)

The memory device of claim 10, further comprising:
a source line contacting the protruding plug.

### Claim 12 (depends on 11)

The memory device of claim 11, wherein the plug comprises:
a blocking layer vertically passing through the interlayer insulation layers and the gate lines;
a charge trap layer formed along an inner wall of the blocking layer;
a tunnel insulation layer formed along an inner wall of the charge trap layer;
a channel layer formed along an inner wall of the tunnel insulation layer; and
a core insulation layer filling a space surrounded by the channel layer.

### Claim 13 (depends on 12)

The memory device of claim 12, wherein the channel layer of the plug contacts the source line.

### Claim 14

A memory device comprising:
interlayer insulation layers and gate lines alternately stacked on each other between bit lines and source lines;
plugs vertically passing through the interlayer insulation layers and the gate lines; and
a first slit vertically passing through the interlayer insulation layers and the gate lines to separate the interlayer insulation layers and the gate lines into different memory blocks,
wherein each of the gate lines includes:
a barrier layer;
a first conductive layer surrounded by the barrier layer; and
a second conductive layer surrounded by the first conductive layer and having a grain size different from a grain size of the first conductive layer, wherein a size of the second conductive layer increases with decreasing distance of the second conductive layer from the first slit.

### Claim 15 (depends on 14)

The memory device of claim 14, wherein the grain size of the second conductive layer is less than the grain size of the first conductive layer.

### Claim 16 (depends on 14)

The memory device of claim 14, wherein the grain size of the first conductive layer is less than the grain size of the second conductive layer.

### Claim 17 (depends on 14)

The memory device of claim 14, wherein the first conductive layer is formed of tungsten (W), and the second conductive layer is formed of molybdenum (Mo).

### Claim 18 (depends on 14)

The memory device of claim 14, wherein the first conductive layer is formed of molybdenum (Mo), and the second conductive layer is formed of tungsten (W).

### Claim 19 (depends on 14)

The memory device of claim 14, wherein a volume of the second conductive layer is changed according to a distance from the first slit.

### Claim 20 (depends on 14)

The memory device of claim 14, further comprising:
a gate separation trench separating each of some gate lines adjacent to the bit lines among the gate lines.

### Claim 21 (depends on 20)

The memory device of claim 20, wherein the gate separation trench is extended along a direction perpendicular to a direction in which the bit lines extend.

### Claim 22 (depends on 15)

The memory device of claim 15, wherein a volume of the second conductive layer decreases with decreasing distance to the gate separation trench.

### Claim 23 (depends on 14)

The memory device of claim 14, further comprising:
a second slit spaced apart from the first slit.

### Claim 24 (depends on 23)

The memory device of claim 23, wherein a volume of the second conductive layer increases with decreasing distance to the first slit or the second slit, and decreases with decreasing distance to a center between the first and second slits.

### Claim 25

A method of manufacturing a memory device, the method comprising:
alternately stacking interlayer insulation layers and sacrificial layers;
forming plugs vertically passing through the interlayer insulation layers and the sacrificial layers;
forming a slit vertically passing through the interlayer insulation layers and the sacrificial layers in a boundary area between different memory blocks;
removing the sacrificial layers exposed through a sidewall of the slit;
forming a first conductive layer in an area from which the sacrificial layers are removed; and
filling a void generated when the first conductive layer is formed with a second conductive layer having a first grain size different from a grain size of the first conductive layer.

### Claim 26 (depends on 25)

The method of claim 25, wherein the grain size of the first conductive layer is less than the grain size of the second conductive layer.

### Claim 27 (depends on 26)

The method of claim 26, wherein the first conductive layer is formed of tungsten (W), and the second conductive layer is formed of molybdenum (Mo).

### Claim 28 (depends on 25)

The method of claim 25, wherein the grain size of the first conductive layer is greater than the grain size of the second conductive layer.

### Claim 29 (depends on 28)

The method of claim 28, wherein the first conductive layer is formed of molybdenum (Mo), and the second conductive layer is formed of tungsten (W).

### Claim 30 (depends on 25)

The method of claim 25, further comprising:
performing a heat treatment process, after filling the void generated when the first conductive layer is formed with the second conductive layer.