# US 2025/0095276 A1 · Enhanced Techniques for Traversing Ray Tracing Acceleration Structures > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2025/0095276 A1 - Document ID: US20250095276A1 - Status: Published application - Kind: A1 - Application number: 18/962,764 - Filed: 2024-11-27 - Published: 2025-03-20 - Earliest claimed: 2020-06-11 - Assignees: NVIDIA Corporation - Applicants: NVIDIA Corporation - Inventors: Gregory MUTHLER; John BURGESS - Web page: https://patentgrep.com/patent/US20250095276A1 ## CPC - G06T 15/06: Ray-tracing - G06F 9/30094: {Condition code generation, e.g. Carry, Zero flag} - G06F 9/5027: {the resource being a machine, e.g. CPUs, Servers, Terminals} - G06T 15/08: Volume rendering - G06T 17/005: {Tree description, e.g. octree, quadtree} - G06T 2210/12: Bounding box - G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Enhanced techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure are disclosed. For example, traversal efficiency is improved by combining programmable traversals based on ray operations with per-node static configurations that modify traversal behavior. The per-node static configurations enable creators of acceleration data structures to optimize for potential traversals without necessarily requiring detailed information about ray characteristics and ray operations used when traversing the acceleration structure. Moreover, by providing for selective exclusion of certain nodes using per-node static configurations, less memory is needed to express an acceleration structure that includes, for example, different geometric levels of details corresponding to a single object. ## Claims ### Claim 1 A ray tracing acceleration hardware device, comprising: memory configured to store an acceleration structure comprising a plurality of nodes, each node of the plurality of nodes comprises a respective programmable ray operation state indicator; ray storage configured to store a ray operation indicator from a ray received from a processor; traversal circuitry configured to traverse the acceleration structure according to the ray, the traversing including, for each node comprising the respective programmable ray operation state indicator, selectively, based on a value of the respective programmable ray operation state indicator of the each node, either performing a ray operation corresponding to the ray operation indicator or not performing the ray operation; and intersection detection circuitry configured to detect one or more intersections of the ray with one or more nodes of the acceleration structure during the traversing and return information of the detected intersection to the processor. ### Claim 2 (depends on 1) The ray tracing acceleration hardware device according to claim 1, wherein each said respective programmable ray operation state indicator has a value of true or false. ### Claim 3 (depends on 1) The ray tracing acceleration hardware device according to claim 1, wherein the acceleration structure comprises a first bottom level acceleration structure (BLAS) and second BLAS, wherein one of the first BLAS and the second BLAS has at least one level of detail (LOD) of geometry that is not in the other of the first BLAS and the second BLAS, and the respective programmable ray operation state indicator of the first BLAS has a value different from that of the respective programmable ray operation state indicator of the second BLAS. ### Claim 4 (depends on 1) The ray tracing acceleration hardware device according to claim 1, wherein said each of one or more node of the plurality of nodes comprising a respective programmable ray operation state indicator is in a respectively different compressed treelet comprising said each node and one or more child nodes of said each node. ### Claim 5 (depends on 4) The ray tracing acceleration hardware device according to claim 4, wherein the one or more child nodes do not store a programmable ray operation state indicator. ### Claim 6 (depends on 1) The ray tracing acceleration hardware device according to claim 1, wherein the not performing the ray operation comprises ignoring the ray operation with respect to said each node. ### Claim 7 (depends on 1) The ray tracing acceleration hardware device according to claim 1, wherein the performing a ray operation corresponding to the ray operation indicator comprises performing the ray operation specified by the ray operation indicator on one or more child nodes of the each node. ### Claim 8 (depends on 1) The ray tracing acceleration hardware device according to claim 1, wherein the performing a ray operation corresponding to the ray operation indicator comprises performing, using the ray operation indicator, at least one parameter specified in the ray other than the ray operation indicator, and at least one parameter specified in a child node of the each node, the ray operation specified by the ray operation indicator. ### Claim 8 (depends on 1) The ray tracing acceleration hardware device according to claim 1, wherein the respective programmable ray operation state indicator is stored in a complet including the each node and one or more child nodes of the each node, and wherein the each node includes a node parameter that is used in the ray operation with one or more other parameters from the ray. ### Claim 9 (depends on 1) The ray tracing acceleration hardware device according to claim 1, wherein the respective programmable ray operation state indicator is set in the each node, and wherein the traversal circuitry is further configured to, if the respective programmable ray operation state indicator is in the second state, determining, based on an invert bit in a child node of the each node, whether or not to traverse the child node without performing the ray operation on the child node. ### Claim 10 (depends on 1) The ray tracing acceleration hardware device according to claim 1, wherein the selectively not performing the ray operation comprises traversing a child node of the each node without performing the ray operation on the child node. ### Claim 11 (depends on 1) The ray tracing acceleration hardware device according to claim 1, wherein the selectively performing the ray operation comprises determining, based on the performed ray operation whether to traverse a child node of the each node, and responsive to a result of the determining either traversing the child node or not traversing the child node. ### Claim 12 (depends on 1) The ray tracing acceleration hardware device according to claim 1, wherein a data structure of the each node includes the respective programmable ray operation state indicator, and wherein the traversal circuitry is further configured to perform the ray operation using the ray operation indicator, and at least one parameter specified in the ray other than the ray operation indicator and/or at least one parameter specified in a child node of the each node. ### Claim 13 (depends on 1) The ray tracing acceleration hardware device according to claim 1, wherein a data structure of the each node includes the respective programmable ray operation state indicator, wherein the respective programmable ray operation state indicator encodes a default action, and wherein the traversal circuitry is further configured to, when the respective programmable ray operation state indicator is in the second state, perform the default action, instead of performing the ray operation, at the each node. ### Claim 13 (depends on 1) The ray tracing acceleration hardware device according to claim 1, wherein the each node is a root node in a compressed treelet and the each node includes a node parameter that is used in the logical operation with one or more parameters from the ray. ### Claim 14 (depends on 1) The ray tracing acceleration hardware device according to claim 1, wherein, whereas the detecting of the one or more intersections is based on x, y and z coordinates associated with the each node of the acceleration structure and the ray, the ray operation is based on parameters other than the x, y and z coordinates associated with the each node and the x, y and z coordinates of the ray. ### Claim 15 (depends on 14) The ray tracing acceleration hardware device according to claim 14, wherein the parameters in the ray includes a length of the ray. ### Claim 16 (depends on 1) The ray tracing acceleration hardware device according to claim 1, wherein the respective programmable ray operation state indicator is set in the each node, and wherein the traversal circuitry is further configured to, if the respective programmable ray operation state indicator has a second value, determining, based on an invert bit in a child node of the each node, whether or not to traverse the child node of the each node without performing the ray operation on the child node. ### Claim 17 (depends on 1) The ray tracing acceleration hardware device according to claim 1, wherein the traversal circuitry and intersection detection circuitry are parts of a server or a data center employed in generating an image, and the image is streamed to a user device. ### Claim 18 (depends on 1) The ray tracing acceleration hardware device according to claim 1, wherein the traversal circuitry and intersection detection circuitry are employed in generating an image, and the image is used for training, testing, or certifying a neural network employed in a machine, robot, or autonomous vehicle. ### Claim 19 A system comprising: a processor configured to generate a ray including a ray operation indicator; and a coprocessor connected to the processor and comprising: memory configured to store an acceleration structure comprising a plurality of nodes, each of one or more node of the plurality of nodes comprises a respective programmable ray operation state indicator; ray storage configured to store the opcode from the ray; traversal circuitry configured to traverse the acceleration structure according to the ray, the traversing including, for each node comprising the respective programmable ray operation state indicator, selectively, based on a value of the respective programmable ray operation state indicator of the each node, either performing a ray operation corresponding to the ray operation indicator or not performing the ray operation; and intersection detection circuitry configured to detect one or more intersections of the ray with one or more nodes of the acceleration structure during the traversing and return information of the detected intersection to the processor. ### Claim 20 A method, comprising: storing in a memory of a hardware coprocessor at least portions of an acceleration structure comprising a compressed treelet including a node, one or more child nodes of the node, and a state indicator associated with the node; receiving, in the hardware coprocessor, a ray from a processor, the ray specifying a ray operation indicator; storing the operation indicator in a ray storage in the hardware coprocessor; traversing, by traversal circuitry in the hardware coprocessor, the acceleration structure according to the ray, the traversing including, for each node comprising the respective programmable ray operation state indicator, selectively, based on a value of the respective programmable ray operation state indicator of the each node, either performing a ray operation corresponding to the ray operation indicator or not performing the ray operation; and detecting, by intersection detection circuitry in the hardware coprocessor, one or more intersections of the ray with one or more nodes of the acceleration structure during the traversing and return information of the detected intersection to the processor.