# US 2025/0095101 A1 · Efficient bi-directional image scaling

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- Number: US 2025/0095101 A1
- Document ID: US20250095101A1
- Status: Published application
- Kind: A1
- Application number: 18/471,255
- Filed: 2023-09-20
- Published: 2025-03-20
- Earliest claimed: 2023-09-20
- Assignees: QUALCOMM Incorporated
- Applicants: QUALCOMM Incorporated
- Inventors: Sriram EMAROSE; Raja Shekhar Reddy ANNAM
- Web page: https://patentgrep.com/patent/US20250095101A1

## CPC

- G06T 3/40: Scaling of whole images or parts thereof, e.g. expanding or contracting
- G06T 1/20: Processor architectures; Processor configuration, e.g. pipelining
- G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL

## Abstract

A processor-implemented method for scaling an image includes receiving a digital image including at least a portion to be scaled. A set of pixels of the portion to be scaled in a horizontal direction is sampled. The sampled set of pixels is bi-directionally scaled by applying a horizontal scaling parameter to the sampled set of pixels to compute a horizontally scaled value. The horizontally scaled value is accumulated until a counter is equal to a vertical scaling parameter. A bi-directionally scaled value is computed by applying the vertical scaling parameter to the accumulated horizontally scaled value. The bi-directionally scaled value is stored.

## Claims

### Claim 1

A processor-implemented method, performed by one or more processors, the processor-implemented method comprising:
receiving a digital image including at least a portion to be scaled;
sampling a set of pixels of the portion to be scaled in a horizontal direction; and
bi-directionally scaling the sampled set of pixels by:
applying a horizontal scaling parameter to the sampled set of pixels to compute a horizontally scaled value;
accumulating the horizontally scaled value until a counter is equal to a vertical scaling parameter;
computing a bi-directionally scaled value by applying the vertical scaling parameter to the accumulated horizontally scaled value; and
storing the bi-directionally scaled value.

### Claim 2 (depends on 1)

The processor-implemented method of claim 1, further comprising repeating the sampling, scaling, and accumulating for each row of the portion to be scaled.

### Claim 3 (depends on 1)

The processor-implemented method of claim 1, further comprising resetting the counter responsive to the counter being equal to the vertical scaling parameter.

### Claim 4 (depends on 1)

The processor-implemented method of claim 1, in which the digital image is vectorized.

### Claim 5 (depends on 1)

The processor-implemented method of claim 1, in which the one or more processors comprise a hardware accelerator.

### Claim 6 (depends on 1)

The processor-implemented method of claim 1, in which the digital image is loaded into memory using a single load operation.

### Claim 7 (depends on 1)

The processor-implemented method of claim 1, in which the bi-directionally scaling comprises an asymmetric scaling.

### Claim 8

An apparatus for processor-implemented method, comprising:
at least one memory; and
at least one processor coupled to the at least one memory, the at least one processor configured to:
receive a digital image including at least a portion to be scaled;
sample a set of pixels of the portion to be scaled in a horizontal direction; and
bi-directionally scale the sampled set of pixels by:
applying a horizontal scaling parameter to the sampled set of pixels to compute a horizontally scaled value;
accumulating the horizontally scaled value until a counter is equal to a vertical scaling parameter;
computing a bi-directionally scaled value by applying the vertical scaling parameter to the accumulated horizontally scaled value; and
storing the bi-directionally scaled value.

### Claim 9 (depends on 8)

The apparatus of claim 8, in which the at least one processor is further configured to repeat the sampling, scaling, and accumulating for each row of the portion to be scaled.

### Claim 10 (depends on 8)

The apparatus of claim 8, in which the at least one processor is further configured to reset the counter responsive to the counter being equal to the vertical scaling parameter.

### Claim 11 (depends on 8)

The apparatus of claim 8, in which the digital image is vectorized.

### Claim 12 (depends on 8)

The apparatus of claim 8, in which the one or more processors comprise a hardware accelerator.

### Claim 13 (depends on 8)

The apparatus of claim 8, in which the at least one processor is further configured to load the digital image into memory using a single load operation.

### Claim 14 (depends on 8)

The apparatus of claim 8, in which the bi-directionally scaling comprises an asymmetric scaling.

### Claim 15

A non-transitory computer-readable medium having program code recorded thereon, the program code executed by one or more processors and comprising:
program code to receive a digital image including at least a portion to be scaled;
program code to sample a set of pixels of the portion to be scaled in a horizontal direction; and
program code to bi-directionally scale the sampled set of pixels by:
applying a horizontal scaling parameter to the sampled set of pixels to compute a horizontally scaled value;
accumulating the horizontally scaled value until a counter is equal to a vertical scaling parameter;
computing a bi-directionally scaled value by applying the vertical scaling parameter to the accumulated horizontally scaled value; and
storing the bi-directionally scaled value.

### Claim 16 (depends on 15)

The non-transitory computer-readable medium of claim 15, in which the program code comprises program code to repeat the sampling, scaling, and accumulating for each row of the portion to be scaled.

### Claim 17 (depends on 15)

The non-transitory computer-readable medium of claim 15, in which the program code comprises program code to reset the counter responsive to the counter being equal to the vertical scaling parameter.

### Claim 18 (depends on 15)

The non-transitory computer-readable medium of claim 15, in which the digital image is vectorized.

### Claim 19 (depends on 15)

The non-transitory computer-readable medium of claim 15, in which the one or more processors comprise a hardware accelerator.

### Claim 20 (depends on 15)

The non-transitory computer-readable medium of claim 15, in which the program code comprises program code to load the digital image into memory using a single load operation.

### Claim 21 (depends on 15)

The non-transitory computer-readable medium of claim 15, in which the program code to bi-directionally scale the sampled set of pixels performs an asymmetric scaling.

### Claim 22

An apparatus for processor-implemented method, comprising:
means for receiving a digital image including at least a portion to be scaled;
means for sampling a set of pixels of the portion to be scaled in a horizontal direction; and
means for bi-directionally scaling the sampled set of pixels by:
applying a horizontal scaling parameter to the sampled set of pixels to compute a horizontally scaled value;
accumulating the horizontally scaled value until a counter is equal to a vertical scaling parameter;
computing a bi-directionally scaled value by applying the vertical scaling parameter to the accumulated horizontally scaled value; and
storing the bi-directionally scaled value.

### Claim 23 (depends on 22)

The apparatus for processor-implemented method of claim 22, further comprising means for repeating the sampling, scaling, and accumulating for each row of the portion to be scaled.

### Claim 24 (depends on 22)

The apparatus for processor-implemented method of claim 22, further comprising means for resetting the counter responsive to the counter being equal to the vertical scaling parameter.

### Claim 25 (depends on 22)

The apparatus for processor-implemented method of claim 22, wherein the digital image is vectorized.

### Claim 26 (depends on 22)

The apparatus for processor-implemented method of claim 22, further comprising means for loading the digital image into memory using a single load operation.