Coprocessors with Bypass Optimization, Variable Grid Architecture, and Fused Vector Operations

A method comprising:

• issuing a given instruction operation, corresponding to a given coprocessor instruction defined in an instruction set of a coprocessor, a plurality of times in a plurality of processing element circuits in the coprocessor, wherein the plurality of processing element circuits is arranged in a first grid of one or more rows and one or more columns, wherein:
• the given coprocessor instruction is defined to cause evaluation of a second plurality of processing element circuits arranged in a second grid of one or more rows and one or more columns, wherein the second grid includes more processing element circuits than the first grid;
• and
• different issuances of the given instruction operation are configured to cause respective different portions of the evaluation defined by the given coprocessor instruction to be performed.

A system comprising:

• a processor configured to process instructions defined by an instruction set;
• and
• a coprocessor coupled to the processor, wherein:
• a subset of the instructions defined by the instruction set are coprocessor instructions executable by the coprocessor;
• the processor is configured to detect a given coprocessor instruction and issue the given coprocessor instruction to the coprocessor for execution;
• and
• the coprocessor comprises:
• a plurality of processing element circuits arranged in a first grid of one or more rows and one or more columns, wherein the given coprocessor instruction is defined in the instruction set to cause evaluation of a second plurality of processing element circuits arranged in a second grid of one or more rows and one or more columns, wherein the second grid includes more processing element circuits than the first grid;
• and
• a scheduler circuit configured to issue instruction operations to the plurality of processing element circuits, wherein the scheduler circuit is configured to issue a given instruction operation corresponding to the given coprocessor instruction a plurality of times to complete the given coprocessor instruction, and wherein different issuances of the given instruction operation are configured to cause respective different portions of the evaluation defined by the given coprocessor instruction to be performed.