# US 2025/0094359 A1 · Fully pipelined read-modify-write support

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- Number: US 2025/0094359 A1
- Document ID: US20250094359A1
- Status: Published application
- Kind: A1
- Application number: 18/966,268
- Filed: 2024-12-03
- Published: 2025-03-20
- Earliest claimed: 2019-05-24
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Naveen BHORIA; Timothy David Anderson; Pete Michael Hippleheuser
- Web page: https://patentgrep.com/patent/US20250094359A1

## CPC

- G06F 12/128: adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
- G06F 9/3001: {Arithmetic instructions}
- G06F 9/30043: {LOAD or STORE instructions; Clear instruction}
- G06F 9/30047: {Prefetch instructions; cache control instructions}
- G06F 9/546: {Message passing systems or structures, e.g. queues}
- G06F 11/1064: {in cache or content addressable memories}
- G06F 12/0215: {with look ahead addressing means}
- G06F 12/0238: {Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory}
- G06F 12/0292: {using tables or multilevel address translation means (G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10)}
- G06F 12/0802: Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F 12/0804: with main memory updating (G06F12/0806 takes precedence)
- G06F 12/0806: Multiuser, multiprocessor or multiprocessing cache systems
- G06F 12/0811: with multilevel cache hierarchies
- G06F 12/0815: Cache consistency protocols
- G06F 12/082: {Associative directories (G06F12/0822 takes precedence)}
- G06F 12/0853: Cache with multiport tag or data arrays
- G06F 12/0855: Overlapped cache accessing, e.g. pipeline (G06F12/0846 takes precedence)
- G06F 12/0864: using pseudo-associative means, e.g. set-associative or hashing
- G06F 12/0884: Parallel mode, e.g. in parallel with main memory or CPU
- G06F 12/0888: using selective caching, e.g. bypass
- G06F 12/0891: using clearing, invalidating or resetting means
- G06F 12/0895: of parts of caches, e.g. directory or tag array
- G06F 12/0897: with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811)
- G06F 12/1027: using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
- G06F 12/12: Replacement control
- G06F 12/121: using replacement algorithms
- G06F 12/126: with special data handling, e.g. priority of data or instructions, handling errors or pinning
- G06F 12/127: using additional replacement algorithms
- G06F 13/1605: {based on arbitration (arbitration in handling access to a common bus or bus system G06F13/36)}
- G06F 13/1642: {with request queuing}
- G06F 13/1673: {using buffers}
- G06F 13/1689: {Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234)}
- G06F 15/8069: {using a cache}
- G11C 5/066: {Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals}
- G11C 7/10: Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C 7/1015: {Read-write modes for single port memories, i.e. having either a random port or a serial port}
- G11C 7/106: {Data output latches}
- G11C 7/1075: {for multiport memories each having random access ports and serial ports, e.g. video RAM}
- G11C 7/1078: {Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits}
- G11C 7/1087: {Data input latches}
- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- G11C 29/42: using error correcting codes [ECC] or parity check
- G11C 29/44: Indication or identification of errors, e.g. for repair
- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- G11C 29/72: {with optimized replacement algorithms}
- G11C 29/76: {using address translation or modifications}
- G06F 2212/1016: Performance improvement
- G06F 2212/1021: Hit rate improvement
- G06F 2212/1024: Latency reduction
- G06F 2212/1041: Resource optimization
- G06F 2212/1044: Space efficiency improvement
- G06F 2212/301: In special purpose processing node, e.g. vector processor
- G06F 2212/454: Vector or matrix data
- G06F 2212/603: of operating mode, e.g. cache mode or local memory mode
- G06F 2212/6032: Way prediction in set-associative cache
- G06F 2212/6042: Allocation of cache space to multiple users or processors
- G06F 2212/608: Details relating to cache mapping
- G06F 2212/62: Details of cache specific to multiprocessor cache arrangements
- G11C 29/4401: {for self repair}
- G11C 2029/0409: {Online test}
- G11C 2029/0411: {Online error correction}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

Methods, apparatus, systems and articles of manufacture are disclosed to facilitate fully pipelined read-modify-write support in level 1 data cache using store queue and data forwarding. An example apparatus includes a first storage, a second storage, a store queue coupled to the first storage and the second storage, the store queue operable to receive a first memory operation specifying a first set of data, process the first memory operation for storing the first set of data in at least one of the first storage and the second storage, receive a second memory operation, and prior to storing the first set of data in the at least one of the first storage and the second storage, feedback the first set of data for use in the second memory operation.

## Claims

### Claim 1

A device comprising:
a cache memory; and
a cache queue coupled to the cache memory and that includes:
a first pipeline stage coupled to the cache memory and configured to, based on a first operation associated with writing a first set of data, read a second set of data;
a second pipeline stage coupled to the first pipeline stage and that includes read-modify-write circuitry configured to merge the first set of data with the second set of data to produce a third set of data; and
a third pipeline stage coupled to the second pipeline stage and configured to, based on a second operation associated with reading the first set of data, cause the third set of data that includes the first set of data to be provided to a previous pipeline stage of the cache queue prior to the third set of data being stored in the cache memory.

### Claim 2 (depends on 1)

The device of claim 1, wherein:
the third pipeline stage includes error correcting code generation circuitry configured to generate error correcting code for the third set of data; and
the third pipeline stage is configured to cause the error correcting code to be stored in the cache memory with the third set of data.

### Claim 3 (depends on 1)

The device of claim 1, wherein the previous pipeline stage is the second pipeline stage.

### Claim 4 (depends on 1)

The device of claim 1, wherein:
the second operation is a read-modify-write operation; and
the third pipeline stage is configured to provide the third set of data to the read-modify-write circuitry of the second pipeline stage.

### Claim 5 (depends on 1)

The device of claim 1, wherein:
the second pipeline stage includes arithmetic circuitry; and
the third pipeline stage is configured to provide the third set of data to the arithmetic circuitry of the second pipeline stage.

### Claim 6 (depends on 1)

The device of claim 1, wherein:
the second pipeline stage includes atomic compare-and-swap circuitry; and
the third pipeline stage is configured to provide the third set of data to the atomic compare-and-swap circuitry of the second pipeline stage.

### Claim 7 (depends on 1)

The device of claim 1, wherein the cache memory is a level-one (L1) main cache memory.

### Claim 8 (depends on 1)

The device of claim 1, wherein the cache memory is a level-one (L1) victim cache memory.

### Claim 9 (depends on 1)

The device of claim 1, wherein the third pipeline stage is configured to provide the third set of data to the first pipeline stage to be stored in the cache memory.

### Claim 10

A device comprising:
a main cache memory;
a victim cache memory; and
a cache queue coupled to the main cache memory and that includes:
a first pipeline stage coupled to the main cache memory and configured to, based on a read-modify-write operation associated with writing a first set of data, read a second set of data;
a second pipeline stage coupled to the first pipeline stage and that includes read-modify-write circuitry configured to merge the first set of data with the second set of data to produce a third set of data; and
a third pipeline stage coupled to the second pipeline stage and configured to, based on a second operation associated with reading the first set of data, cause the third set of data to be provided to a previous pipeline stage of the cache queue prior to the third set of data being stored in the main cache memory.

### Claim 11 (depends on 10)

The device of claim 10, wherein:
the third pipeline stage includes error correcting code generation circuitry configured to generate error correcting code for the third set of data; and
the third pipeline stage is configured to cause the error correcting code to be stored in the main cache memory with the third set of data.

### Claim 12 (depends on 10)

The device of claim 10, wherein the previous pipeline stage is the second pipeline stage.

### Claim 13 (depends on 10)

The device of claim 10, wherein:
the second operation is a read-modify-write operation; and
the third pipeline stage is configured to provide the third set of data to the read-modify-write circuitry of the second pipeline stage.

### Claim 14 (depends on 10)

The device of claim 10, wherein:
the second pipeline stage includes arithmetic circuitry; and
the third pipeline stage is configured to provide the third set of data to the arithmetic circuitry of the second pipeline stage.

### Claim 15 (depends on 10)

The device of claim 10, wherein:
the second pipeline stage includes atomic compare-and-swap circuitry; and
the third pipeline stage is configured to provide the third set of data to the atomic compare-and-swap circuitry of the second pipeline stage.

### Claim 16

A device comprising:
a main cache memory;
a victim cache memory; and
a cache queue coupled to the victim cache memory and that includes:
a first pipeline stage coupled to the victim cache memory and configured to, based on a read-modify-write operation associated with writing a first set of data, read a second set of data;
a second pipeline stage coupled to the first pipeline stage and that includes read-modify-write circuitry configured to merge the first set of data with the second set of data to produce a third set of data; and
a third pipeline stage coupled to the second pipeline stage and configured to, based on a second operation associated with reading the first set of data, cause the third set of data to be provided to a previous pipeline stage of the cache queue prior to the third set of data being stored in the victim cache memory.

### Claim 17 (depends on 16)

The device of claim 16, wherein:
the third pipeline stage includes error correcting code generation circuitry configured to generate error correcting code for the third set of data; and
the third pipeline stage is configured to cause the error correcting code to be stored in the victim cache memory with the third set of data.

### Claim 18 (depends on 16)

The device of claim 16, wherein:
the second operation is a read-modify-write operation; and
the third pipeline stage is configured to provide the third set of data to the read-modify-write circuitry of the second pipeline stage.

### Claim 19 (depends on 16)

The device of claim 16, wherein:
the second pipeline stage includes arithmetic circuitry; and
the third pipeline stage is configured to provide the third set of data to the arithmetic circuitry of the second pipeline stage.

### Claim 20 (depends on 16)

The device of claim 16, wherein:
the second pipeline stage includes atomic compare-and-swap circuitry; and
the third pipeline stage is configured to provide the third set of data to the atomic compare-and-swap circuitry of the second pipeline stage.