# US 2025/0094355 A1 · Translation Lookaside Buffer Entry Locking > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2025/0094355 A1 - Document ID: US20250094355A1 - Status: Published application - Kind: A1 - Application number: 18/544,110 - Filed: 2023-12-18 - Published: 2025-03-20 - Earliest claimed: 2023-09-18 - Assignees: Apple Inc. - Applicants: Apple Inc. - Inventors: Brett S. Feero; Brian T. Mokrzycki; Jonathan Y. Tong; Michael D. Snyder; James N. Hardage - Web page: https://patentgrep.com/patent/US20250094355A1 ## CPC - G06F 12/1027: using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] - G06F 2212/1024: Latency reduction - G06F 2212/68: Details of translation look-aside buffer [TLB] - G06F 2212/683: Invalidation - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Techniques are disclosed relating to using an instruction (e.g., a pre-translate instruction) to lock translations in TLB entries. The execution of the instruction may include storing translation information in a TLB entry, and setting an indication that the entry is locked. The processor circuitry may receive an invalidate command corresponding to the locked entry. Processor circuitry may, in response to the invalidate command and based on the indication that the entry is locked, maintain the locked entry in a valid state in the translation lookaside buffer circuitry, notwithstanding the invalidate command. Processor circuitry may be further configured to modify previously-stored data in a given entry to aggregate, in the entry, translation information for multiple regions of the second address space. ## Claims ### Claim 1 An apparatus, comprising: processor circuitry that includes: lock control circuitry; and translation lookaside buffer circuitry that implements entries for translations from a first address space to a second address space; wherein: the processor circuitry is configured to decode and execute an instruction, wherein the execution includes to: store translation information in an entry of the translation lookaside buffer circuitry; and set, by the lock control circuitry, an indication that the entry is locked; and the processor circuitry is configured to, in response to an invalidate command corresponding to the locked entry, access the indication and maintain the locked entry in a valid state in the translation lookaside buffer circuitry, notwithstanding the invalidate command, based on the indication. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the instruction is a translation lookaside buffer pre-translate instruction. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein: the processor circuitry is configured to provide a guarantee, based on the set indication that the entry is locked, that latency for one or more operations that access the locked entry does not exceed a threshold latency value. ### Claim 4 (depends on 1) The apparatus of claim 1, further comprising: read control circuitry configured to provide information that indicates lock status of one or more entries in the translation lookaside buffer circuitry in a software-accessible control register. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein to store the translation information in the entry, the processor circuitry is configured to modify previously-stored data in the entry to aggregate, in the entry, translation information for multiple regions of the second address space. ### Claim 6 (depends on 5) The apparatus of claim 5, wherein modification of the previously-stored data includes modification of a page size field of the entry. ### Claim 7 (depends on 5) The apparatus of claim 5, wherein the processor circuitry is configured to perform the aggregation in response to verifying one or more aggregation criteria. ### Claim 8 (depends on 7) The apparatus of claim 7, wherein the one or more aggregation criteria include contiguity criteria, including: a first contiguity criterion that the translation information corresponds to a first set of addresses in the first address space that is contiguous with a second set of addresses in the first address space associated with the instruction; and a second contiguity criterion that the translation information corresponds to a first set of addresses in the second address space that is contiguous with a second set of addresses in the second address space associated with the instruction. ### Claim 9 (depends on 5) The apparatus of claim 5, wherein the translation lookaside buffer circuitry includes: a first set of entries, including the entry, that support translations for variable region sizes in the second address space; and a second set of entries that support translations for fixed region sizes in the second address space. ### Claim 10 (depends on 1) The apparatus of claim 1, wherein the maintenance of the locked entry in a valid state in the translation lookaside buffer circuitry is further based on a locked-entry-invalidation policy currently imposed by the apparatus. ### Claim 11 (depends on 10) The apparatus of claim 10, wherein the processor circuitry supports at least the following locked-entry-invalidation policies: a first policy under which no invalidate operations are allowed to invalidate locked entries; and a second policy under which only invalidate operations that specify an address in the first address space that matches a given locked entry is allowed to invalidate the given locked entry. ### Claim 12 (depends on 1) The apparatus of claim 1, wherein the processor circuitry is further configured to, in response to an invalidate operation with an address in the first address space that corresponds to a first portion of a region in the second address space corresponding to the locked entry, modify data in the entry to provide a translation for a second portion of the region and not the first portion of the region. ### Claim 13 (depends on 1) The apparatus of claim 1, further comprising control circuitry configured to unlock multiple locked entries in the translation lookaside buffer circuitry based on software input. ### Claim 14 (depends on 1) The apparatus of claim 1, wherein the first address space is a virtual address space, and the second address space is a physical address space of a memory circuit of the apparatus. ### Claim 15 (depends on 1) The apparatus of claim 1, wherein the apparatus is further configured to generate the instruction based on a criticality of data in the first address space, where the data is addressed by the translation information. ### Claim 16 A non-transitory computer-readable medium having an instruction stored thereon that is executable by a computing device to perform operations comprising: setting, in an entry of translation lookaside buffer circuitry, translation information for translations from a first address space to a second address space; and setting an indication that the entry is locked, such that, in response to an invalidate command corresponding to the locked entry, the computing device maintains the locked entry in a valid state in the translation lookaside buffer circuitry, notwithstanding the invalidate command, based on the indication. ### Claim 17 (depends on 16) The non-transitory computer-readable medium of claim 16, wherein the instruction is a translation lookaside buffer pre-translate instruction. ### Claim 18 (depends on 16) The non-transitory computer-readable medium of claim 16, wherein the setting further comprises accessing, using a software-accessible control register, the indication that the entry is locked. ### Claim 19 (depends on 16) The non-transitory computer-readable medium of claim 16, wherein the operations further comprise: modifying set translation information to aggregate, in the entry, translation information for multiple regions of the second address space. ### Claim 20 A method, comprising: decoding and executing, by a computing device, an instruction, wherein the executing includes: storing, in an entry of a translation lookaside buffer circuitry, translation information for translations from a first address space to a second address space; setting, by lock control circuitry, an indication that the entry is locked; and in response to an invalidate command corresponding to the locked entry, accessing the indication and maintaining the locked entry in a valid state in the translation lookaside buffer circuitry, notwithstanding the invalidate command, based on the indication. ### Claim 21 (depends on 20) The method of claim 20, wherein the instruction is a translation lookaside buffer pre-translate instruction. ### Claim 22 (depends on 20) The method of claim 20, wherein the storing further comprises modifying previously stored data in the entry to aggregate translation information for multiple regions of the second address space. ### Claim 23 (depends on 20) The method of claim 20, wherein the maintenance of the locked entry in a valid state in the translation lookaside buffer circuitry is further based on a locked-entry-invalidation policy currently imposed by the computing device.