# US 2025/0094342 A1 · Design verification process for bit spreading error resistant memory system

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2025/0094342 A1
- Document ID: US20250094342A1
- Status: Published application
- Kind: A1
- Application number: 18/470,111
- Filed: 2023-09-19
- Published: 2025-03-20
- Earliest claimed: 2023-09-19
- Assignees: BAE Systems Information and Electronic Systems Integration Inc.
- Applicants: BAE SYSTEMS Information and Electronic Systems Integration Inc.
- Inventors: Jeffrey E. Robertson
- Web page: https://patentgrep.com/patent/US20250094342A1

## CPC

- G06F 12/0292: {using tables or multilevel address translation means (G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10)}
- G06F 11/1044: {with specific ECC/EDC distribution}
- G06F 12/0284: {Multiple user address space allocation, e.g. using different base addresses (interprocessor communication G06F15/163)}
- G06F 30/323: Translation or migration, e.g. logic to logic, hardware description language [HDL] translation or netlist translation
- G06F 30/3308: using simulation
- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- G06F 2212/1008: Correctness of operation, e.g. memory ordering
- G06F 2212/1032: Reliability improvement, data loss prevention, degraded operation etc
- G06F 2212/403: Error protection encoding, e.g. using parity or ECC codes
- G06F 2212/7201: Logical to physical mapping or translation of blocks or pages
- G11C 2029/0411: {Online error correction}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Techniques are provided for design verification of a bit spreading memory. A methodology implementing the techniques according to an embodiment includes using a bit spreading geometry file to convert a logical address of the memory to a physical address. The geometry file defines a scheme by which bits of a data word stored at the logical address are spread over multiple RAMs. The method also includes writing data bits of a test data word to the physical address, causing a design simulator to simulate a read from the logical address, and comparing the result to the test data word for verification. The method further includes causing the design simulator to simulate a write of the test data word to the logical address, reading data bits from the physical address, arranging the bits into a retrieved data word, and comparing the test data word to the retrieved data word for verification.

## Claims

### Claim 1

A computer program product including one or more non-transitory machine-readable mediums encoded with instructions that when executed by one or more processors cause a process to be carried out for verification of a design of a memory, the process comprising:
using a bit spreading geometry file to convert a logical address of the memory to a physical address, wherein the bit spreading geometry file defines a bit spreading scheme by which data bits of a data word stored at the logical address are stored in a spread fashion over a plurality of random access memories (RAMs) of the memory;
writing data bits of a test data word to the physical address;
causing a design simulator to simulate a read from the logical address; and
comparing a result of the simulated read to the test data word to verify the design of the memory.

### Claim 2 (depends on 1)

The computer program product of claim 1, wherein the process further comprises:
causing the design simulator to simulate a write of the test data word to the logical address;
reading data bits from the physical address;
arranging the data bits to form a retrieved data word; and
comparing the test data word to the retrieved data word to further verify the design of the memory.

### Claim 3 (depends on 1)

The computer program product of claim 1, wherein the bit spreading geometry file is configured to specify a logical base address of the memory, a size of the memory, and a description of the each of the plurality of RAMs.

### Claim 4 (depends on 3)

The computer program product of claim 3, wherein the description of the each of the plurality of RAMs includes a number of blocks of the RAM, a number of bits of each of the blocks of the RAM, and an identifying label of the RAM.

### Claim 5 (depends on 1)

The computer program product of claim 1, wherein the process iterates over additional logical addresses.

### Claim 6 (depends on 1)

The computer program product of claim 1, wherein the design of the memory is represented as a register transfer level description configured for execution by the design simulator.

### Claim 7 (depends on 1)

The computer program product of claim 1, wherein the process is implemented in Verilog and conforms to a Universal Verification Methodology.

### Claim 8

A method for verification of a design of a memory, the method comprising:
using, by a processor-based system, a bit spreading geometry file to convert a logical address of the memory to a physical address, wherein the bit spreading geometry file defines a bit spreading scheme by which data bits of a data word stored at the logical address are stored in a spread fashion over a plurality of random access memories (RAMs) of the memory;
writing, by the processor-based system, data bits of a test data word to the physical address;
causing, by the processor-based system, a design simulator to simulate a read from the logical address; and
comparing, by the processor-based system, a result of the simulated read to the test data word to verify the design of the memory.

### Claim 9 (depends on 8)

The method of claim 8, further comprising:
causing the design simulator to simulate a write of the test data word to the logical address;
reading data bits from the physical address;
arranging the data bits to form a retrieved data word; and
comparing the test data word to the retrieved data word to further verify the design of the memory.

### Claim 10 (depends on 8)

The method of claim 8, wherein the bit spreading geometry file is configured to specify a logical base address of the memory, a size of the memory, and a description of the each of the plurality of RAMs.

### Claim 11 (depends on 10)

The method of claim 10, wherein the description of the each of the plurality of RAMs includes a number of blocks of the RAM, a number of bits of each of the blocks of the RAM, and an identifying label of the RAM.

### Claim 12 (depends on 8)

The method of claim 8, wherein the method iterates over additional logical addresses.

### Claim 13 (depends on 8)

The method of claim 8, wherein the design of the memory is represented as a register transfer level description configured for execution by the design simulator.

### Claim 14 (depends on 8)

The method of claim 8, wherein the method is implemented in Verilog and conforms to a Universal Verification Methodology.

### Claim 15

A method for verification of a design of a memory, the method comprising:
using, by a processor-based system, a bit spreading geometry file to convert a logical address of the memory to a physical address, wherein the bit spreading geometry file defines a bit spreading scheme by which data bits of a data word stored at the logical address are stored in a spread fashion over a plurality of random access memories (RAMs) of the memory;
causing, by the processor-based system, a design simulator to simulate a write of a test data word to the logical address of the memory;
reading, by the processor-based system, data bits from the physical address;
arranging, by the processor-based system, the data bits to form a retrieved data word; and
comparing, by the processor-based system, the test data word to the retrieved data word to verify the design of the memory.

### Claim 16 (depends on 15)

The method of claim 15, further comprising:
writing data bits of the test data word to the physical address;
causing the design simulator to simulate a read from the logical address; and
comparing a result of the simulated read to the test data word to further verify the design of the memory.

### Claim 17 (depends on 15)

The method of claim 15, wherein the bit spreading geometry file is configured to specify a logical base address of the memory, a size of the memory, and a description of the each of the plurality of RAMs.

### Claim 18 (depends on 17)

The method of claim 17, wherein the description of the each of the plurality of RAMs includes a number of blocks of the RAM, a number of bits of each of the blocks of the RAM, and an identifying label of the RAM.

### Claim 19 (depends on 15)

The method of claim 15, wherein the method iterates over additional logical addresses.

### Claim 20 (depends on 15)

The method of claim 15, wherein the design of the memory is represented as a register transfer level description configured for execution by the design simulator and the method is implemented in Verilog and conforms to a Universal Verification Methodology.