# US 2025/0094341 A1 · Techniques for accessing managed nand > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2025/0094341 A1 - Document ID: US20250094341A1 - Status: Published application - Kind: A1 - Application number: 18/896,407 - Filed: 2024-09-25 - Published: 2025-03-20 - Earliest claimed: 2021-01-22 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Junjun Wang; Yi Heng Sun - Web page: https://patentgrep.com/patent/US20250094341A1 ## CPC - G06F 12/0253: {Garbage collection, i.e. reclamation of unreferenced memory} - G06F 12/0238: {Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory} - G06F 12/0653: {with centralised address assignment} - G06F 2212/1044: Space efficiency improvement - G06F 2212/7209: Validity control, e.g. using flags, time stamps or sequence numbers - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Methods, systems, and devices for techniques for accessing managed not-AND (NAND) memory are described. An indicator of a first type that indicates whether each physical address in a group of physical addresses stores valid data may be accessed. Indicators of a second type may be used to indicate whether respective physical addresses of the group of physical addresses store valid data. Data stored at the group of physical addresses may be transferred to a different group of physical addresses based on the indicator of the first type. Also, another indicator of the first type that indicates whether each physical address in the different group of physical addresses stores valid data may be updated. ## Claims ### Claim 1 (canceled) ### Claim 2 A memory system, comprising: one or more memory devices; and processing circuitry coupled with the one or more memory devices and configured to cause the memory system to: access a bit of a first validity table that indicates whether each physical address of a set of physical addresses stores valid data; and determine whether to access a second validity table in response to determining whether the bit in the first validity table indicates that data stored at the set of physical addresses is valid or invalid. ### Claim 3 (depends on 2) The memory system of claim 2, wherein the processing circuitry is further configured to cause the memory system to: refrain from accessing the second validity table in response to determining that the bit in the first validity table indicates that the data stored at the set of physical addresses is valid. ### Claim 4 (depends on 3) The memory system of claim 3, wherein the processing circuitry is further configured to cause the memory system to: transfer data stored at the set of physical addresses to a second set of physical addresses in response to determining that the first validity table indicates valid data for the set of physical addresses and accessing the first validity table; and update the first validity table in response to transferring the data. ### Claim 5 (depends on 2) The memory system of claim 2, wherein the processing circuitry is further configured to cause the memory system to: access a plurality of bits of the second validity table in response to determining that the bit in the first validity table indicates that the data stored at the set of physical addresses is invalid, wherein each bit of the plurality of bits of the second validity table indicates whether a respective physical address of the set of physical addresses stores valid data. ### Claim 6 (depends on 5) The memory system of claim 5, wherein the processing circuitry is further configured to cause the memory system to: determine whether to transfer data for each bit of the plurality of bits based at least in part on a value of each bit of the plurality of bits; and transfer data stored at a subset of the set of physical addresses to a second set of physical addresses in response to determining that each bit of the subset of the plurality of bits indicates that the respective physical address stores valid data. ### Claim 7 (depends on 2) The memory system of claim 2, wherein a first block comprises the set of physical addresses. ### Claim 8 (depends on 7) The memory system of claim 7, wherein the set of physical addresses is associated with one or more pages of the first block. ### Claim 9 (depends on 2) The memory system of claim 2, wherein a first bit of the first validity table indicates whether each physical address of the set of physical addresses stores valid data for a set of sequential logical addresses. ### Claim 10 A memory system, comprising: one or more memory devices; and processing circuitry coupled with the one or more memory devices and configured to cause the memory system to: receive a program command indicating data to be programmed during a program operation; program, during the program operation, the data to one or more memory cells in accordance with the program command, the programming comprising storing the data at one or more groups of physical addresses of the one or more memory cells; update a first validity table to indicate that each group of physical addresses of the one or more groups of physical addresses programmed during the program operation stores valid data; and update a second validity table in accordance with updating the first validity table. ### Claim 11 (depends on 10) The memory system of claim 10, wherein, to update the first validity table, the one or more memory devices are configured to cause the memory system to: set or retain, for each group of physical addresses of the one or more groups of physical addresses, one or more bits in the first validity table to indicate that each physical address of the group stores valid data, wherein updating the second validity table is in accordance with setting the one or more bits for each group in the first validity table. ### Claim 12 (depends on 11) The memory system of claim 11, wherein, to update the second validity table, the one or more memory devices are configured to cause the memory system to: set or retain, for each physical address of each group of the one or more groups of physical addresses, one or more bits of the second validity table to indicate that the physical address stores invalid data, the one or more bits for each group in the first validity table overriding the one or more bits for each physical address of the group in the second validity table. ### Claim 13 (depends on 10) The memory system of claim 10, wherein the processing circuitry is further configured to cause the memory system to: unmap second data associated with one or more second groups of physical addresses; update, in response to unmapping the second data, the first validity table to indicate that one or more physical addresses of the one or more second groups of physical addresses are storing invalid data; and update, in response to unmapping the second data, the second validity table in accordance with updating the first validity table to indicate which physical addresses of the one or more second groups of physical addresses are storing valid data. ### Claim 14 (depends on 10) The memory system of claim 10, wherein the processing circuitry is further configured to cause the memory system to: rewrite second data associated with the one or more groups of physical addresses; update, in response to the rewriting, the first validity table to indicate that one or more physical addresses of the one or more groups of physical addresses are storing invalid data; and update, in response to the rewriting, the second validity table in accordance with updating the first validity table to indicate which physical addresses of the one or more groups of physical addresses are storing valid data. ### Claim 15 (depends on 10) The memory system of claim 10, wherein the processing circuitry is further configured to cause the memory system to: transfer, as part of a garbage collection operation and in accordance with accessing the first validity table, the second validity table, or both, at least a portion of the data stored at the one or more groups of physical addresses to one or more second groups of physical addresses; and update, in accordance with the garbage collection operation, the first validity table, the second validity table, or both, in response to transferring the data. ### Claim 16 A non-transitory computer-readable medium storing code comprising instructions which, when executed by processing circuitry of an electronic device, cause the electronic device to: access a bit of a first validity table that indicates whether each physical address of a set of physical addresses stores valid data; and determine whether to access a second validity table in response to determining whether the bit in the first validity table indicates that data stored at the set of physical addresses is valid or invalid. ### Claim 17 (depends on 16) The non-transitory computer-readable medium of claim 16, wherein the instructions, when executed by the processing circuitry of the electronic device, further cause the electronic device to: refrain from accessing the second validity table in response to determining that the bit in the first validity table indicates that the data stored at the set of physical addresses is valid. ### Claim 18 (depends on 17) The non-transitory computer-readable medium of claim 17, wherein the instructions, when executed by the processing circuitry of the electronic device, further cause the electronic device to: transfer data stored at the set of physical addresses to a second set of physical addresses in response to determining that the first validity table indicates valid data for the set of physical addresses and accessing the first validity table; and update the first validity table in response to transferring the data. ### Claim 19 (depends on 16) The non-transitory computer-readable medium of claim 16, wherein the instructions, when executed by the processing circuitry of the electronic device, further cause the electronic device to: access a plurality of bits of the second validity table in response to determining that the bit in the first validity table indicates that the data stored at the set of physical addresses is invalid, wherein each bit of the plurality of bits of the second validity table indicates whether a respective physical address of the set of physical addresses stores valid data. ### Claim 20 (depends on 19) The non-transitory computer-readable medium of claim 19, wherein the instructions, when executed by the processing circuitry of the electronic device, further cause the electronic device to: determine whether to transfer data for each bit of the plurality of bits in response to determining whether each bit of the plurality of bits indicates that the respective physical address stores valid data; and transfer data stored at a subset of the set of physical addresses to a second set of physical addresses in response to determining that each bit of the subset of the plurality of bits indicates that the respective physical address stores valid data. ### Claim 21 (depends on 16) The non-transitory computer-readable medium of claim 16, wherein a first block comprises the set of physical addresses, and wherein the set of physical addresses is associated with one or more pages of the first block.