# US 2025/0094331 A1 · Electronic devices, memory systems, and power control methods

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- Number: US 2025/0094331 A1
- Document ID: US20250094331A1
- Status: Published application
- Kind: A1
- Application number: 18/392,682
- Filed: 2023-12-21
- Published: 2025-03-20
- Earliest claimed: 2023-09-18
- Assignees: Yangtze Memory Technologies Co., Ltd.
- Applicants: Yangtze Memory Technologies Co., Ltd.
- Inventors: Youxin HE
- Web page: https://patentgrep.com/patent/US20250094331A1

## CPC

- G06F 12/0246: {in block erasable memory, e.g. flash memory}
- G06F 1/26: Power supply means, e.g. regulation thereof (for memories G11C)
- G06F 1/3275: {Power saving in memory, e.g. RAM, cache}
- G06F 3/061: {Improving I/O performance}
- G06F 3/0625: {Power saving in storage systems}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

The present disclosure discloses an electronic device, a memory system and a power control method, which belong to the field of storage technology. A disclosed electronic device can comprise a host and a memory system. The host can comprise a power management unit, and a first interface configured to send an identifier indicating a peak power capability supported by the power management unit. The memory system can comprise at least one memory device coupled with the host, a second interface communicated with the first interface and configured to receive the identifier, and a memory controller coupled the memory device and configured to determine a peak power management policy matches the peak power capability according to the identifier.

## Claims

### Claim 1

A memory system, including:
a memory device coupled with a host;
a second interface communicated with a first interface of the host; and
a memory controller coupled with the memory device and configured to:
receive, through the second interface from the first interface of the host, an identifier indicating a peak power capability supported by the host, and
determine a peak power management policy matches the peak power capability according to the identifier.

### Claim 2 (depends on 1)

The memory system of claim 1, wherein the identifier includes at least one of:
a first identifier representing a first current magnitude that a power management unit of the host is capable of providing to the memory device at a first voltage; and
a second identifier representing a second current magnitude that the power management unit of the host is capable of providing to the memory controller at a second voltage.

### Claim 3 (depends on 1)

The memory system of claim 1, wherein the memory controller is further configured to:
replacing a default peak power management policy preset in the memory controller with the determined peak power management policy.

### Claim 4 (depends on 3)

The memory system of claim 3, wherein the memory controller is further configured to:
in response to determining that the host fails to send the identifier, maintain the default peak power management policy; and
in response to failing to determine the peak power management policy matches the peak power capability according to the identifier, maintain the default peak power management policy.

### Claim 5 (depends on 1)

The memory system of claim 1, wherein the determined peak power management policy includes one or more parameters of controlling the memory system.

### Claim 6 (depends on 5)

The memory system of claim 5, wherein:
the one or more parameters include at least one of a clock frequency, parallelism of the memory device, and an operation latency of an I/O request.

### Claim 7 (depends on 1)

The memory system of claim 1, wherein:
the memory system includes a flash universal storage (UFS) memory system; and
each of the first interface and the second interface includes a UFS interface.

### Claim 8 (depends on 7)

The memory system of claim 7, wherein the identifier is carried in an extended field of a UFS data packet.

### Claim 9 (depends on 2)

The memory system of claim 2, wherein the power management unit includes a power management integrated circuit (PMIC).

### Claim 10 (depends on 1)

The memory system of claim 1, wherein the memory controller is further configured to:
send, through the second interface to the first interface of the host, a response message indicating that the identifier has been received by the memory controller.

### Claim 11 (depends on 1)

The memory system of claim 1, wherein the memory controller is further configured to:
receive, through the second interface from the first interface of the host, an input/output (I/O) request; and
control the memory device to process the I/O request according to the determined peak power management policy.

### Claim 12

An electronic device, including:
a host comprising:
a power management unit, and
a first interface configured to send an identifier indicating a peak power capability supported by the power management unit; and
a memory system comprising:
a memory device,
a second interface communicated with the first interface and configured to receive the identifier, and
a memory controller coupled between the memory device and the host, and configured to determine a peak power management policy matches the peak power capability according to the identifier.

### Claim 13 (depends on 12)

The electronic device of claim 12, wherein the identifier includes at least one of:
a first identifier representing a first current magnitude that a power management unit of the host is capable of providing to the memory device at a first voltage; and
a second identifier representing a second current magnitude that the power management unit of the host is capable of providing to the memory controller at a second voltage.

### Claim 14 (depends on 12)

The electronic device of claim 12, wherein the memory controller is further configured to:
replacing a default peak power management policy preset in the memory controller with the determined peak power management policy;
in response to determining that the host fails to send the identifier, maintain the default peak power management policy; and
in response to failing to determine the peak power management policy matches the peak power capability according to the identifier, maintain the default peak power management policy.

### Claim 15 (depends on 12)

The electronic device of claim 12, wherein:
the determined peak power management policy includes one or more parameters of controlling the memory system; and
the one or more control parameters include at least one of a clock frequency, parallelism of the memory device, and an operation latency of an I/O request.

### Claim 16 (depends on 12)

The electronic device of claim 12, wherein:
the memory system includes a flash universal storage (UFS) memory system;
each of the first interface and the second interface includes a UFS interface;
the identifier is carried in an extended field of a UFS data packet; and
the power management unit includes a power management integrated circuit (PMIC).

### Claim 17 (depends on 12)

The electronic device of claim 12, wherein the memory controller is further configured to:
send, through the second interface to the first interface of the host, a response message indicating that the identifier has been received by the memory controller;
receive, through the second interface from the first interface of the host, an input/output (I/O) request; and
control the memory device to process the I/O request according to the determined peak power management policy.

### Claim 18

A power controlling method, comprising:
sending, through a first interface of a host, an identifier indicating a peak power capability supported by the host;
receiving, by a second interface of a memory system communicated with the first interface, the identifier;
determining, by a memory controller of the memory system, a peak power management policy matches the peak power capability according to the identifier; and
applying, by the memory controller, the peak power management policy to control the memory system.

### Claim 19 (depends on 18)

The method of claim 18, wherein the identifier includes at least one of:
a first identifier representing a first current magnitude that a power management unit of the host is capable of providing to the memory device at a first voltage; and
a second identifier representing a second current magnitude that the power management unit of the host is capable of providing to the memory controller at a second voltage.

### Claim 20 (depends on 18)

The method of claim 18, further comprising:
replacing, by the memory controller, a default peak power management policy with the determined peak power management policy.