# US 2025/0094221 A1 · Thread scheduling for multithreaded data processing environments > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2025/0094221 A1 - Document ID: US20250094221A1 - Status: Published application - Kind: A1 - Application number: 18/970,449 - Filed: 2024-12-05 - Published: 2025-03-20 - Earliest claimed: 2018-03-14 - Assignees: Texas Instruments Incorporated - Applicants: Texas Instruments Incorporated - Inventors: Kedar Chitnis; Mihir Narendra Mody; Jesse Gregory Villarreal, JR.; Lucas Carl Weaver; Brijesh Jadav; Niraj Nandan - Web page: https://patentgrep.com/patent/US20250094221A1 ## CPC - G06F 9/4881: {Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues} - G06F 9/4887: {involving deadlines, e.g. rate based, periodic} - G06F 9/50: Allocation of resources, e.g. of the central processing unit [CPU] - G06F 9/544: {Buffers; Shared memory; Pipes} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement thread scheduling for multithreaded data processing environments are disclosed. Example thread schedulers disclosed herein for a data processing system include a buffer manager to determine availability of respective buffers to be acquired for respective processing threads implementing respective functional nodes of a processing flow, and to identify first ones of the processing threads as stalled due to unavailability of at least one buffer in the respective buffers to be acquired for the first ones of the processing threads. Disclosed example thread schedulers also include a thread execution manager to initiate execution of second ones of the processing threads that are not identified as stalled. ## Claims ### Claim 1 A system comprising: a memory; a first buffer; a second buffer; and a thread scheduler circuit coupled to the memory, the first buffer, and the second buffer, wherein the thread scheduler circuit is configurable to: determine that the first buffer is unavailable for a first thread by checking the memory; store a first stall state for the first thread in the memory in response to determining that the first buffer is unavailable; determine that the second buffer for a second thread is available in response to determining that the first buffer is unavailable; and initiate execution of the second thread in response to determining that the second buffer is available. ### Claim 2 (depends on 1) The system of claim 1, wherein the memory is configured to maintain the first stall state for the first buffer, and wherein the first stall state indicates that the first thread is stalled. ### Claim 3 (depends on 2) The system of claim 2, wherein to store the first stall state, the thread scheduler circuit is configurable to log an identifier for the first thread to a state maintained in the memory for the first buffer. ### Claim 4 (depends on 1) The system of claim 1, wherein to determine that the second buffer is available, the thread scheduler circuit is configurable to check the memory for a state of the second buffer. ### Claim 5 (depends on 1) The system of claim 1, wherein the memory is configured to store a list of threads that are stalled waiting for buffers to become available. ### Claim 6 (depends on 1) The system of claim 1, wherein the memory is configured to store a data structure indicating previously stalled threads that have become unstalled due to a buffer being released. ### Claim 7 (depends on 6) The system of claim 6, wherein the data structure stored in the memory also indicates threads that are not stalled and have not been previously stalled. ### Claim 8 (depends on 6) The system of claim 6, wherein the memory is configured to store a list of threads that are stalled, and wherein the thread scheduler circuit is configurable to: determine that the first buffer has become available; retrieve a thread identifier for the first thread from the list of threads that are stalled; and write the thread identifier for the first thread to the data structure. ### Claim 9 (depends on 8) The system of claim 8, wherein the thread scheduler circuit is configurable to: determine that the first buffer has become available in response to receiving a signal from the first buffer; and determine that the thread identifier is associated with the first stall state stored in the memory after receiving the signal from the first buffer. ### Claim 10 (depends on 1) The system of claim 1, wherein the thread scheduler circuit is configurable to store an indication that the second buffer is unavailable to the memory in response to initiating execution of the second thread. ### Claim 11 (depends on 1) The system of claim 1, wherein the thread scheduler circuit is configurable to: determine that the second buffer is unavailable for a third thread by checking the memory after initiating execution of the second thread; and store a second stall state for the third thread in the memory in response to determining that the second buffer is unavailable. ### Claim 12 (depends on 1) The system of claim 1, wherein the thread scheduler circuit is configurable to: determine a third thread that was stalled due to unavailability of the second buffer after the execution of the second thread is complete; and add the third thread to a data structure stored in the memory to indicate that the third thread is unstalled in response to determining that the third thread that was stalled. ### Claim 13 (depends on 1) The system of claim 1, wherein the thread scheduler circuit is configurable to update a state of the second buffer in the memory to indicate that the second buffer is available after the execution of the second thread is complete. ### Claim 14 A method comprising: determining that a first buffer is unavailable for a first thread by checking a memory; storing a first stall state for the first thread in the memory in response to determining that the first buffer is unavailable; determining that a second buffer for a second thread is available in response to determining that the first buffer is unavailable; and initiating execution of the second thread in response to determining that the second buffer is available. ### Claim 15 (depends on 14) The method of claim 14, further comprising: determining that the first buffer has become available; retrieving a thread identifier for the first thread from a list of threads that are stalled stored in the memory; and writing the thread identifier for the first thread to a data structure stored in the memory indicating previously stalled threads have become unstalled due to a buffer being released. ### Claim 16 (depends on 15) The method of claim 15, further comprising: determining that the first buffer has become available in response to receiving a signal from the first buffer; and determining that the thread identifier is associated with the first stall state stored in the memory after receiving the signal from the first buffer. ### Claim 17 (depends on 14) The method of claim 14, further comprising: determining that the second buffer is unavailable for a third thread by checking the memory after initiating execution of the second thread; and storing a second stall state for the third thread in the memory in response to determining that the second buffer is unavailable. ### Claim 18 (depends on 14) The method of claim 14, further comprising: determining a third thread that was stalled due to unavailability of the second buffer after the execution of the second thread is complete; and adding the third thread to a data structure stored in the memory to indicate that the third thread is unstalled in response to determining that the third thread that was stalled. ### Claim 19 (depends on 14) The method of claim 14, further comprising updating a state of the second buffer in the memory to indicate that the second buffer is available after the execution of the second thread is complete. ### Claim 20 A system comprising: a first buffer; a memory configured to store: a first state for the first buffer; a list of threads that are stalled; and a data structure indicating previously stalled threads that have become unstalled due to a respective buffer being released; and a thread scheduler circuit coupled to the memory and to the first buffer, wherein the thread scheduler circuit is configurable to: determine that the first buffer is unavailable for a first thread by checking the first state in the memory; store a thread identifier for the first thread to the list of threads that are stalled in response to determining that the first buffer is unavailable; determine that the first buffer has become available after storing the thread identifier for the first thread to the list of threads that are stalled; and write the thread identifier for the first thread to the data structure.