# US 2025/0094091 A1 · Read data alignment

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- Number: US 2025/0094091 A1
- Document ID: US20250094091A1
- Status: Published application
- Kind: A1
- Application number: 18/968,260
- Filed: 2024-12-04
- Published: 2025-03-20
- Earliest claimed: 2022-10-18
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Yu-Sheng Hsu; Chihching Chen
- Web page: https://patentgrep.com/patent/US20250094091A1

## CPC

- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0688: {Non-volatile semiconductor memory arrays}
- G06F 3/0604: {Improving or facilitating administration, e.g. storage management}
- G06F 3/0611: {in relation to response time}
- G06F 3/0683: {Plurality of storage devices}
- G06F 13/1689: {Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234)}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Systems, apparatuses, and methods related to a controller architecture for read data alignment are described. An example method can include sending a first notification from a physical layer to each of a number of memory controllers, wherein the first notification indicates that the physical layer and/or a memory device coupled to the physical layer is busy, and blocking commands on each of the number of memory controllers in response to receiving the first notification to cause read data alignment. The method can also include sending a second notification from the physical layer to each of the number of memory controllers, wherein the second notification indicates that the physical layer and/or the memory device coupled to the physical layer is no longer busy, and resuming processing commands on each of the number of memory controllers in response to receiving the second notification.

## Claims

### Claim 1

A method, comprising:
sending a first notification from a physical layer to each of a number of memory controllers, wherein the first notification indicates that the physical layer and/or a memory device coupled to the physical layer is busy; and
blocking commands on each of the number of memory controllers in response to receiving the first notification to cause read data alignment.

### Claim 2 (depends on 1)

The method of claim 1, further including sending the first notification on a side band bus.

### Claim 3 (depends on 1)

The method of claim 1, further including sending the first notification from the physical layer to a logic gate that routes the first notification to each of the number of memory controllers.

### Claim 4 (depends on 1)

The method of claim 1, further including sending an acknowledgement from one of the number of memory controllers to the physical layer in response to receiving the first notification.

### Claim 5 (depends on 1)

The method of claim 1, further including performing a training operation on the physical layer while the commands are blocked on each of the number of memory controllers.

### Claim 6 (depends on 1)

The method of claim 1, further including sending a second notification from the physical layer to each of the number of memory controllers, wherein the second notification indicates that the physical layer and/or the memory device coupled to the physical layer is no longer busy.

### Claim 7 (depends on 6)

The method of claim 6, further including resuming processing commands on each of the number of memory controllers in response to receiving the second notification.

### Claim 8 (depends on 1)

The method of claim 1, wherein each of the number memory controllers is associated with one of a number of physical layers and further including performing a training operation on each of the number of physical layers while the commands are blocked on each of the number of memory controllers.

### Claim 9

A method, comprising:
sending a first notification from a physical layer to each of a number of memory controllers, wherein the first notification indicates that the physical layer has completed a training operation and is no longer busy; and
resuming processing commands on each of the number of memory controllers in response to receiving the second notification.

### Claim 10 (depends on 9)

The method of claim 9, further including sending the first notification on a side band bus.

### Claim 11 (depends on 9)

The method of claim 9, further including sending the first notification from the physical layer to a logic gate that routes the first notification to each of the number of memory controllers.

### Claim 12 (depends on 9)

The method of claim 9, further including sending an acknowledgement from one of the number of memory controllers to the physical layer in response to receiving the first notification.

### Claim 13 (depends on 9)

The method of claim 9, receiving a command at each of the number of memory controllers and performing the command on each of the number of memory controllers in response to receiving the first notification at each of the number of memory controllers.

### Claim 14

An apparatus, comprising:
a central controller;
a number of memory controllers coupled to the central controller via a data bus and a command bus, wherein each of the number of memory controllers include one of a number of physical layers; and
a number of memory devices, wherein each particular memory device of the number of memory devices is coupled to a particular memory controller of the number of memory controllers, wherein the apparatus is configured to:
send a first notification from a physical layer of the number of physical layers to each of the number of memory controllers, wherein the first notification indicates that the physical layer and/or a memory device of the number of memory devices coupled to the physical layer is busy; and
block commands on each of the number of memory controllers in response to receiving the first notification.

### Claim 15 (depends on 14)

The apparatus of claim 14, wherein the first notification is sent from the physical layer to each of the number of memory controllers on a side band bus.

### Claim 16 (depends on 14)

The apparatus of claim 14, wherein the first notification is sent from the physical layer to a logic gate that routes the first notification to each of the number of memory controllers.

### Claim 17 (depends on 14)

The apparatus of claim 14, wherein a training operation is performed on the physical layer while the commands are blocked on the number of memory controllers.

### Claim 18 (depends on 14)

The apparatus of claim 14, wherein the apparatus is configured to send a second notification from the physical layer to each of the number of memory controllers, wherein the second notification indicates that the physical layer and/or the memory device coupled to the physical layer is no longer busy.

### Claim 19 (depends on 18)

The apparatus of claim 18, wherein the apparatus is configured to resume processing commands on each of the number of memory controllers in response to receiving the second notification.

### Claim 20 (depends on 19)

The apparatus of claim 19, wherein each of the number of memory controllers are configured to perform a command received from the central controller in response to receiving the second notification at each of the number of memory controllers