# US 2025/0094086 A1 · Techniques for firmware enhancement in memory devices > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2025/0094086 A1 - Document ID: US20250094086A1 - Status: Published application - Kind: A1 - Application number: 18/896,781 - Filed: 2024-09-25 - Published: 2025-03-20 - Earliest claimed: 2022-07-14 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Zhengbo Wang; Jia Sun; Ming Ma - Web page: https://patentgrep.com/patent/US20250094086A1 ## CPC - G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling} - G06F 3/0604: {Improving or facilitating administration, e.g. storage management} - G06F 3/061: {Improving I/O performance} - G06F 3/0655: {Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices} - G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]} - G06F 12/0246: {in block erasable memory, e.g. flash memory} - G06F 12/063: {for I/O modules, e.g. memory mapped I/O (I/O protocol G06F13/42)} - G06F 3/0656: {Data buffering arrangements} - G06F 2212/7201: Logical to physical mapping or translation of blocks or pages - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Methods, systems, and devices for techniques for firmware enhancement in memory devices are described. A memory system may include a volatile memory device and a non-volatile memory device, which may store a node address mapping. A host system in communication with the memory system may transmit a command instructing the memory system to transfer at least a portion of the node address mapping from the non-volatile memory device to the volatile memory device. The memory system may transmit a response to the command to the host system indicating a status associated with transferring the portion of the node address mapping. ## Claims ### Claim 1 (canceled) ### Claim 2 An apparatus, comprising: processing circuitry configured to cause the apparatus to: select a portion of a node address mapping stored in a first area of a non-volatile memory device of a memory system, the memory system having the non-volatile memory device and a volatile memory device; transmit a command to transfer the portion of the node address mapping to the volatile memory device that is associated with firmware of the memory system, the node address mapping comprising one or more addresses associated with node blocks of a second area of the non-volatile memory device; and receive a response to the command, the response indicating a status associated with transferring the portion. ### Claim 3 (depends on 2) The apparatus of claim 2, wherein the status comprises a successful status indicating that the memory system transferred the portion of the node address mapping to the volatile memory device. ### Claim 4 (depends on 2) The apparatus of claim 2, wherein the status comprises a busy status indicating that the memory system is processing one or more operations associated with one or more commands sent prior to the command to transfer the portion. ### Claim 5 (depends on 2) The apparatus of claim 2, wherein the status comprises a failed status indicating that the memory system failed to transfer the portion of the node address mapping. ### Claim 6 (depends on 5) The apparatus of claim 5, wherein the processing circuitry is further configured to cause the apparatus to: transmit a second command to transfer the portion of the node address mapping to the volatile memory device in response to receiving the response to the command indicating the failed status. ### Claim 7 (depends on 5) The apparatus of claim 5, wherein the processing circuitry is further configured to cause the apparatus to: receive an indication of one or more parameters associated with the failed status in the response, the one or more parameters associated with an illegal request, a hardware error, a power threshold, or any combination thereof. ### Claim 8 (depends on 2) The apparatus of claim 2, wherein the processing circuitry is further configured to cause the apparatus to: fill one or more fields of the command in response to selecting the portion of the node address mapping, the one or more fields indicating the portion of the node address mapping. ### Claim 9 (depends on 8) The apparatus of claim 8, wherein the one or more fields indicate a range of addresses associated with the node address mapping or a portion of the range of addresses. ### Claim 10 (depends on 2) The apparatus of claim 2, wherein the processing circuitry is further configured to cause the apparatus to: transmit a second command to remove a second portion of the node address mapping from the volatile memory device. ### Claim 11 (depends on 2) The apparatus of claim 2, wherein the command comprises an indication of a type of information associated with the portion of the node address mapping. ### Claim 12 (depends on 2) The apparatus of claim 2, wherein the processing circuitry is further configured to cause the apparatus to: identify that the portion of the node address mapping corresponds to a frequency of access operations that satisfies a threshold, wherein selecting the portion is in accordance with the satisfied threshold. ### Claim 13 An apparatus, comprising: a non-volatile memory device configured to store data of the apparatus, the non-volatile memory device comprising a plurality of areas each associated with respective ranges of addresses; a volatile memory device coupled with firmware of the apparatus; and a controller operable to transfer a portion of a node address mapping stored in a first area of the non-volatile memory device from the non-volatile memory device to the volatile memory device, the node address mapping comprising one or more addresses associated with node blocks of a second area of the plurality of areas. ### Claim 14 (depends on 13) The apparatus of claim 13, wherein the non-volatile memory device is associated with a file system layout, the file system layout indicating an index for each area of the plurality of areas, the plurality of areas comprising the first area storing the node address mapping, the second area storing data associated with a host system, a third area storing checkpoint data, a fourth area storing a segment information table, a fifth area storing a segment summary area, or any combination thereof. ### Claim 15 A non-transitory computer-readable medium storing code comprising instructions which, when executed by processing circuitry of an electronic device, cause the electronic device to: select a portion of a node address mapping stored in a first area of a non-volatile memory device of a memory system, the memory system having the non-volatile memory device and a volatile memory device; transmit a command to transfer the portion of the node address mapping to the volatile memory device that is associated with firmware of the memory system, the node address mapping comprising one or more addresses associated with node blocks of a second area of the non-volatile memory device; and receive a response to the command, the response indicating a status associated with transferring the portion. ### Claim 16 (depends on 15) The non-transitory computer-readable medium of claim 15, wherein the status comprises a successful status indicating that the memory system transferred the portion of the node address mapping to the volatile memory device. ### Claim 17 (depends on 15) The non-transitory computer-readable medium of claim 15, wherein the status comprises a busy status indicating that the memory system is processing one or more operations associated with one or more commands sent prior to the command to transfer the portion. ### Claim 18 (depends on 15) The non-transitory computer-readable medium of claim 15, wherein the status comprises a failed status indicating that the memory system failed to transfer the portion of the node address mapping. ### Claim 19 (depends on 18) The non-transitory computer-readable medium of claim 18, wherein the instructions, when executed by the processing circuitry of the memory system, further cause the memory system to: transmit a second command to transfer the portion of the node address mapping to the volatile memory device in response to receiving the response to the command indicating the failed status. ### Claim 20 (depends on 18) The non-transitory computer-readable medium of claim 18, wherein the instructions, when executed by the processing circuitry of the memory system, further cause the memory system to: receive an indication of one or more parameters associated with the failed status in the response, the one or more parameters associated with an illegal request, a hardware error, a power threshold, or any combination thereof. ### Claim 21 (depends on 15) The non-transitory computer-readable medium of claim 15, wherein the instructions, when executed by the processing circuitry of the memory system, further cause the memory system to: fill one or more fields of the command in response to selecting the portion of the node address mapping, the one or more fields indicating the portion of the node address mapping.