# US 2025/0094080 A1 · Non-volatile memory module architecture to support memory error correction

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- Number: US 2025/0094080 A1
- Document ID: US20250094080A1
- Status: Published application
- Kind: A1
- Application number: 18/959,106
- Filed: 2024-11-25
- Published: 2025-03-20
- Earliest claimed: 2016-01-19
- Assignees: Lodestar Licensing Group LLC
- Applicants: Lodestar Licensing Group, LLC
- Inventors: George Pax; Jonathan Scott Parry
- Web page: https://patentgrep.com/patent/US20250094080A1

## CPC

- G06F 3/0656: {Data buffering arrangements}
- G06F 3/061: {Improving I/O performance}
- G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors}
- G06F 3/0685: {Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays}
- G06F 3/0688: {Non-volatile semiconductor memory arrays}
- G06F 11/1068: {in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence)}
- G06F 11/1072: {in multilevel memories}
- G06F 12/0246: {in block erasable memory, e.g. flash memory}
- G11C 5/04: Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports
- G11C 5/141: {Battery and back-up supplies}
- G11C 7/10: Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C 8/00: Arrangements for selecting an address in a digital store (for stores using transistors G11C11/407, G11C11/413)
- G11C 11/005: {comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells}
- G11C 16/32: Timing circuits
- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- G11C 29/883: {using a single defective memory device with reduced capacity, e.g. half capacity}
- G06F 2212/1032: Reliability improvement, data loss prevention, degraded operation etc
- G06F 2212/7202: Allocation control and policies
- G11C 2029/0409: {Online test}
- G11C 2029/0411: {Online error correction}
- G11C 2207/2245: Memory devices with an internal cache buffer
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

Apparatus and methods are provided for operating a non-volatile memory module. In an example, a method can include filling a first plurality of pages of a first non-volatile memory with first data from a first data lane that includes a first volatile memory device, and filling a second plurality of pages of the first non-volatile memory device with second data from a second data lane that includes a second volatile memory device. In certain examples, the first plurality of pages does not include data from the second data lane.

## Claims

### Claim 1

An apparatus, comprising:
volatile memory;
non-volatile memory coupled to the volatile memory; and
a controller configured to:
receive, from a host device, a control signal having a first state;
in response to the first state, restore previously-stored data from the non-volatile memory to the volatile memory;
indicate, to the host device, an error in restoring the previously-stored data; and
operate the volatile memory in response to a request based on the error from the host device.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the error is associated with non-volatile hardware.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein the previously-stored data comprises error correction code (ECC) information.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein the controller is configured to communicate with the host device via a buffer, and wherein the controller is disposed on a different die than the host device.

### Claim 5 (depends on 4)

The apparatus of claim 4, comprising a plurality of buffers coupled to the host device, wherein the plurality of buffers comprises the buffer.

### Claim 6 (depends on 1)

The apparatus of claim 1, comprising a flash memory corresponding to the non-volatile memory.

### Claim 7 (depends on 1)

The apparatus of claim 1, wherein the controller is configured to indicate the error in a memory region accessible to the host device.

### Claim 8 (depends on 1)

The apparatus of claim 1, wherein the controller is configured to:
receive an additional control signal from the host device; and
initiate transfer of data from the volatile memory to the non-volatile memory based on the additional control signal.

### Claim 9 (depends on 8)

The apparatus of claim 8, wherein the additional control signal indicates a power loss.

### Claim 10

A tangible, non-transitory, computer-readable medium comprising instructions that, when executed by processing circuitry, causes a memory controller to perform operations comprising:
receiving, from a host device, a control signal having a first state;
in response to the first state, restoring previously-stored data from non-volatile memory to volatile memory;
indicating, to the host device, an error in restoring the previously-stored data; and
operating a memory module in response to a request based on the error from the host device.

### Claim 11 (depends on 10)

The tangible, non-transitory, computer-readable medium of claim 10, wherein the first state corresponds to a return of power to the volatile memory.

### Claim 12 (depends on 10)

The tangible, non-transitory, computer-readable medium of claim 10, wherein indicating the error comprises indicating the error via a buffer accessible to the host device.

### Claim 13 (depends on 10)

The tangible, non-transitory, computer-readable medium of claim 10, wherein restoring the previously-stored data comprises generating one or more memory-based read signals, one or more memory-based write signals, or both.

### Claim 14 (depends on 10)

The tangible, non-transitory, computer-readable medium of claim 10, comprising:
receiving an additional control signal from the host device; and
initiating transfer of data from the volatile memory to the non-volatile memory based on the additional control signal.

### Claim 15

A method, comprising:
receiving, at a memory module from a host device, a control signal having a first state based on a return of power to the memory module;
in response to the first state, restoring previously-stored data from non-volatile memory to volatile memory;
indicating, to the host device, an error in restoring the previously-stored data; and
operating the memory module in response to a request based on the error from the host device.

### Claim 16 (depends on 15)

The method of claim 15, comprising initiating a transfer of data from the non-volatile memory to the volatile memory based on the control signal having the first state.

### Claim 17 (depends on 15)

The method of claim 15, wherein indicating the error comprises indicating the error via a buffer accessible to the host device.

### Claim 18 (depends on 15)

The method of claim 15, wherein restoring the previously-stored data comprises performing memory-based controller read and write operations relative to flash memory comprising the non-volatile memory.

### Claim 19 (depends on 15)

The method of claim 15, comprising:
receiving an additional control signal from the host device; and
initiating transfer of data from the volatile memory to the non-volatile memory based on the additional control signal.

### Claim 20 (depends on 19)

The method of claim 19, wherein the additional control signal indicates a power loss.