# US 2025/0094079 A1 · Smart dimm multiport memory system

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- Number: US 2025/0094079 A1
- Document ID: US20250094079A1
- Status: Published application
- Kind: A1
- Application number: 18/969,085
- Filed: 2024-12-04
- Published: 2025-03-20
- Earliest claimed: 2020-02-24
- Assignees: Sunrise Memory Corporation
- Applicants: Sunrise Memory Corporation
- Inventors: Robert D. Norman
- Web page: https://patentgrep.com/patent/US20250094079A1

## CPC

- G06F 3/0655: {Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices}
- G11C 7/1039: {using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers}
- G06F 3/061: {Improving I/O performance}
- G06F 3/0673: {Single storage device}
- G06F 13/1657: {Access to multiple memories}
- G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)}
- G11C 5/04: Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports
- G11C 7/1075: {for multiport memories each having random access ports and serial ports, e.g. video RAM}
- G11C 11/412: using field-effect transistors only
- G11C 11/417: for memory cells of the field-effect type
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A memory structure including three-dimensional NOR memory strings and method of fabrication is disclosed. In one embodiment, a memory system includes a set of memory modules, each memory module including one or more quasi-volatile memory circuits interconnected to at least one memory controller where each memory module includes a set of memory ports; a DIMM controller and processor in communication with each of the memory modules; and multiple processor ports to be coupled to respective processing units external to the memory system. The memory ports of each memory module are coupled to the processor ports and to the DIMM controller and processor so that each memory module is accessible by respective processing units that are coupled to the processor ports and by the DIMM controller and process.

## Claims

### Claim 1

A memory system, comprising:
a plurality of memory modules, each memory module comprising one or more quasi-volatile memory circuits interconnected to at least one memory controller, each memory module comprising a plurality of memory ports;
a DIMM controller and processor in communication with each of the plurality of memory modules; and
a plurality of processor ports to be coupled to respective processing units external to the memory system,
wherein the plurality of memory ports of each memory module are coupled to the plurality of processor ports and to the DIMM controller and processor so that each memory module is accessible by respective processing units that are coupled to the plurality of processor ports and by the DIMM controller and processor.

### Claim 2 (depends on 1)

The memory system of claim 1, wherein the plurality of processor ports include a first processor port and a second processor port, each memory module being accessible by processing units that are coupled to the first processor port and the second processor port and by the DIMM controller and processor.

### Claim 3 (depends on 1)

The memory system of claim 1, wherein the plurality of memory modules are operated simultaneously in response to commands received at the plurality of processor ports and the DIMM controller and processor.

### Claim 4 (depends on 1)

The memory system of claim 1, wherein, within each memory module, each quasi-volatile memory circuit is organized in a plurality of memory banks and the plurality of memory banks are operated simultaneously in response to commands received at the plurality of memory ports.

### Claim 5 (depends on 4)

The memory system of claim 4, wherein, within each memory module, different memory banks in the plurality of memory banks are operated simultaneously in response to commands received at each of the plurality of memory ports.

### Claim 6 (depends on 4)

The memory system of claim 4, wherein the plurality of memory ports of each memory module carry out memory accesses in parallel.

### Claim 7 (depends on 1)

The memory system of claim 1, wherein each memory module comprises the one or more quasi-volatile memory circuits each formed on a separate semiconductor substrate and interconnected with each other, and the at least one memory controller circuit also formed on a semiconductor substrate separate from the semiconductor substrates of the quasi-volatile memory circuits and interconnected to one of the quasi-volatile memory circuits, and wherein the at least one memory controller circuit operates the quasi-volatile memory circuits as one or more quasi-volatile memories.

### Claim 8 (depends on 7)

The memory system of claim 7, wherein the one or more quasi-volatile memory circuits on separate semiconductor substrates are formed as stacked semiconductor dies and interconnected with each other by through-silicon vias formed in the semiconductor substrates, and wherein the memory controller circuit is interconnected to one of the quasi-volatile memory circuits.

### Claim 9 (depends on 8)

The memory system of claim 8, wherein the memory controller circuit is interconnected to one of the quasi-volatile memory circuits through hybrid bonds.

### Claim 10 (depends on 1)

The memory system of claim 1, wherein the plurality of memory modules comprises partitions of a memory cell array of a quasi-volatile memory device.

### Claim 11 (depends on 1)

The memory system of claim 1, wherein the DIMM controller and processor comprises one or more DIMM interface port, the DIMM interface port being accessible by a processing unit to enable communication with another DIMM or another instance of the memory system.

### Claim 12 (depends on 1)

The memory system of claim 1, wherein each quasi-volatile memory circuit comprises memory cells having a data retention time that enables the memory system to operate at a refresh rate greater than every 64 milliseconds.

### Claim 13 (depends on 1)

The memory system of claim 1, wherein each quasi-volatile memory circuit comprises three-dimensional arrays of NOR-type memory strings formed over a semiconductor substrate.

### Claim 14 (depends on 1)

The memory system of claim 1, wherein, within each memory module, each quasi-volatile memory circuit is organized in a plurality of tiles and the plurality of tiles are operated simultaneously in response to commands received at the plurality of memory ports.

### Claim 15 (depends on 14)

The memory system of claim 14, wherein each tile in the plurality of tiles comprises a three-dimensional array of NOR-type memory strings formed over a semiconductor substrate.

### Claim 16 (depends on 15)

The memory system of claim 15, wherein support circuitry for operating each tile is formed in the semiconductor substrate under each tile.