# US 2025/0094052 A1 · Memory device and operating method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2025/0094052 A1 - Document ID: US20250094052A1 - Status: Published application - Kind: A1 - Application number: 18/605,982 - Filed: 2024-03-15 - Published: 2025-03-20 - Earliest claimed: 2023-09-20 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: SUK-HYUN LIM - Web page: https://patentgrep.com/patent/US20250094052A1 ## CPC - G06F 3/0611: {in relation to response time} - G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling} - G06F 3/0673: {Single storage device} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A memory device according to some embodiments includes a plurality of memory banks, a plurality of registers, a data I/O buffer configured to transmit and receive data, and a control logic configured to receive a low latency bit and an address that is preset according to a type of the data. The control logic is configured to determine a logic level of the low latency bit. Based on the low latency bit, the control logic is configured to store the data in a memory bank corresponding to the address among the plurality of memory banks or a register corresponding to the address among the plurality of registers or reads the data from the memory bank corresponding to the address or the register corresponding to the address. ## Claims ### Claim 1 A memory device comprising: a plurality of memory banks; a plurality of registers; a data I/O buffer configured to transmit and receive data; and a control logic configured to receive a low latency bit and an address that is preset according to a type of the data, wherein the control logic is configured to determine a logic level of the low latency bit, and wherein, based on the low latency bit, the memory device is configured to store the data in a memory bank corresponding to the address among the plurality of memory banks or a register corresponding to the address among the plurality of registers, or configured to read the data from the memory bank corresponding to the address or the register corresponding to the address. ### Claim 2 (depends on 1) The memory device of claim 1, further comprising: a register control logic that is configured to be activated when the low latency bit is at a first level and is configured to perform a register write operation to store the data in the plurality of registers and is configured to perform a register read operation to read the data from the plurality of registers, wherein, when the low latency bit is at a second level that is different from the first level, the control logic is configured to store the data in the memory bank corresponding to the address or configured to read the data from the memory bank corresponding to the address. ### Claim 3 (depends on 2) The memory device of claim 2, wherein when the register write operation is performed, the register control logic is configured to map the address to at least one register address among a plurality of register addresses and is configured to generate a mapping table including a mapping relationship between the address and the register address. ### Claim 4 (depends on 3) The memory device of claim 3, wherein when the register write operation is performed, and when the data has a first size and the register corresponding to the address has a second size greater than the first size, the register control logic is configured to map the address to one of the plurality of register addresses. ### Claim 5 (depends on 3) The memory device of claim 3, wherein when the register write operation is performed, and when the data has a first size and the register corresponding to the address has a second size greater than the first size, the register control logic is configured to map the address to register addresses among the plurality of register addresses. ### Claim 6 (depends on 3) The memory device of claim 3, further comprising: a deserializer that is electrically or logically connected to the plurality of registers and is configured to generate parallel data by parallelizing input data, wherein the data I/O buffer is configured to transfer external data to the deserializer based on an input/output control signal, and wherein the parallel data is stored in the plurality of registers. ### Claim 7 (depends on 3) The memory device of claim 3, wherein when the register read operation is performed, the register control logic is configured to transmit a control signal that indicates to the control logic to read the data from the memory bank corresponding to the address when the register address corresponding to the address does not exist in the mapping table. ### Claim 8 (depends on 3) The memory device of claim 3, wherein when the register read operation is performed, the register control logic is configured to read the data from at least one register corresponding to the at least one register address that is mapped to the address based on the mapping table. ### Claim 9 (depends on 1) The memory device of claim 1, further comprising: a plurality of memory dies; and a buffer die, wherein the plurality of memory dies comprises at least one memory bank among the plurality of memory banks, wherein the buffer die comprises the plurality of registers and the control logic, and wherein the plurality of memory dies are stacked on the buffer die and are interconnected to one another by a plurality of through silicon vias. ### Claim 10 A memory device comprising: a buffer die configured to transmit and receive data to and from a host device, wherein the buffer die includes a plurality of registers; a plurality of memory dies that are stacked on the buffer die, wherein the plurality of memory dies include a plurality of memory banks; and a plurality of through silicon vias that electrically connect the buffer die to respective ones of the plurality of memory dies, wherein the buffer die further comprises a control logic configured to receive a low latency bit and an address that is preset according to a type of the data, wherein the control logic is configured to determine a logic level of the low latency bit, and wherein, based on the low latency bit, the memory device is configured to store the data in a memory bank corresponding to the address among the plurality of memory banks or store the data in a register corresponding to the address among the plurality of registers, or read the data from the memory bank corresponding to the address or the register corresponding to the address. ### Claim 11 (depends on 10) The memory device of claim 10, wherein the buffer die further comprises a plurality of static random access memories (SRAMs) configured to store the data. ### Claim 12 (depends on 10) The memory device of claim 10, wherein each of the plurality of memory dies includes at least one of a dynamic random access memory (DRAM), a thyristor random access memory (TRAM), a static random access memory (SRAM), or a double data rate synchronous dynamic random access memory (DDR SDRAM). ### Claim 13 (depends on 10) The memory device of claim 10, wherein the buffer die further includes a register control logic that is configured to be activated when the low latency bit is at a first level and is configured to perform a register write operation to store the data in the plurality of registers and is configured to perform a register read operation to read the data from the plurality of registers, and wherein, when the low latency bit is at a second level that is different from the first level, the control logic is configured to store the data in the memory bank corresponding to the address or configured to read the data from the memory bank corresponding to the address. ### Claim 14 (depends on 13) The memory device of claim 13, wherein when the register write operation is performed, the register control logic is configured to map the address to at least one register address among a plurality of register addresses based on a size of the data and a size of each of the plurality of registers, and is configured to generate a mapping table including a mapping relationship between the address and the register address. ### Claim 15 (depends on 14) The memory device of claim 14, wherein when the register read operation is performed, the register control logic is configured to read the data from at least one register corresponding to the at least one register address mapped to the address based on the mapping table. ### Claim 16 An operating method of a memory device, comprising: receiving, by a memory device that comprises a buffer die including a plurality of registers and at least one memory die stacked on the buffer die and including a plurality of memory banks, data, a low latency bit that is preset according to a type of the data, a command, and an address from a host device; and determining a logic level of the low latency bit, wherein when the command is a write command, the operating method of the memory device comprises: mapping the address to at least one register address among a plurality of register addresses when the logic level of the low latency bit is at a first level; generating a mapping table including a mapping relationship between the address and the register address; and storing the data in a register corresponding to the mapped register address. ### Claim 17 (depends on 16) The operating method of claim 16, wherein when the command is the write command and the logic level of the low latency bit is at a second level that is different from the first level, the operating method of the memory device further comprises storing the data in a memory bank corresponding to the address among the plurality of memory banks. ### Claim 18 (depends on 16) The operating method of claim 16, wherein the mapping of the address comprises mapping the address to at least one register address among the plurality of register addresses based on a size of the data and respective sizes of each of the plurality of registers. ### Claim 19 (depends on 16) The operating method of claim 16, wherein when the command is a read command, the operating method of the memory device further comprises: determining whether a register address mapped to the address exists within a mapping table when the logic level of the low latency bit is at a first level; and reading the data from a register corresponding to the register address when the mapped register address exists. ### Claim 20 (depends on 19) The operating method of claim 19, wherein when the mapped register address does not exist, the operating method of the memory device further comprises: reading the data from a memory bank corresponding to the address among the plurality of memory banks.