# US 2025/0094044 A1 · Multicore shared cache operation engine

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- Number: US 2025/0094044 A1
- Document ID: US20250094044A1
- Status: Published application
- Kind: A1
- Application number: 18/963,043
- Filed: 2024-11-27
- Published: 2025-03-20
- Earliest claimed: 2018-10-15
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Kai Chirca; Matthew David Pierson; David E. Smith; Timothy David Anderson
- Web page: https://patentgrep.com/patent/US20250094044A1

## CPC

- G06F 11/1004: {to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00)}
- G06F 3/0604: {Improving or facilitating administration, e.g. storage management}
- G06F 3/0607: {by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device}
- G06F 3/0632: {by initialisation or re-initialisation of storage systems}
- G06F 3/064: {Management of blocks}
- G06F 3/0658: {Controller construction arrangements}
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0673: {Single storage device}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F 9/30101: {Special purpose registers}
- G06F 9/30123: {according to context, e.g. thread buffers}
- G06F 9/3897: {with adaptable data path}
- G06F 9/4881: {Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues}
- G06F 9/5016: {the resource being the memory}
- G06F 12/0607: {Interleaved addressing}
- G06F 12/0811: with multilevel cache hierarchies
- G06F 12/0815: Cache consistency protocols
- G06F 12/0828: {with concurrent directory accessing, i.e. handling multiple concurrent coherency transactions}
- G06F 12/0831: using a bus scheme, e.g. with bus monitoring or watching means
- G06F 12/084: with a shared cache
- G06F 12/0855: Overlapped cache accessing, e.g. pipeline (G06F12/0846 takes precedence)
- G06F 12/0857: {by multiple requestors}
- G06F 12/0875: with dedicated cache, e.g. instruction or stack
- G06F 12/0891: using clearing, invalidating or resetting means
- G06F 12/10: Address translation
- G06F 12/1009: using page tables, e.g. page table structures
- G06F 13/124: {where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine}
- G06F 13/1642: {with request queuing}
- G06F 13/1663: {Access to shared memory}
- G06F 13/1668: {Details of memory controller}
- G06F 13/4027: {using bus bridges (G06F13/4022 takes precedence)}
- H03M 13/015: {Simulation or testing of codes, e.g. bit error rate [BER] measurements}
- H03M 13/098: {using single parity bit}
- H03M 13/1575: {Direct decoding, e.g. by a direct determination of the error locator polynomial from syndromes and subsequent analysis or by matrix operations involving syndromes, e.g. for codes with a small minimum Hamming distance}
- H03M 13/276: {Interleaving address generation}
- H03M 13/2785: {Interleaver using in-place interleaving, i.e. writing to and reading from the memory is performed at the same memory location}
- G06F 12/0833: {in combination with broadcast means (e.g. for invalidation or updating)}
- G06F 12/0846: Cache with multiple tag or data arrays being simultaneously accessible
- G06F 12/0851: {Cache with interleaved addressing}
- G06F 12/0862: with prefetch
- G06F 2212/1008: Correctness of operation, e.g. memory ordering
- G06F 2212/1016: Performance improvement
- G06F 2212/1024: Latency reduction
- G06F 2212/1048: Scalability
- G06F 2212/304: In main memory subsystem
- G06F 2212/452: Instruction code
- G06F 2212/6024: History based prefetching
- G06F 2212/657: Virtual address space management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

Techniques including receiving configuration information for a trigger control channel of the one or more trigger control channels, the configuration information defining a first one or more triggering events, receiving a first memory management command, store the first memory management command, detecting a first one or more triggering events, and triggering the stored first memory management command based on the detected first one or more triggering events.

## Claims

### Claim 1

A system comprising:
an interface; and
a controller coupled to the interface and configurable to:
receive a first memory command via the interface to perform a first memory operation;
receive a first event from the interface; and
output the first memory command to perform the first memory operation in response the first event.

### Claim 2 (depends on 1)

The system of claim 1, further comprising a system bus coupled to the interface.

### Claim 3 (depends on 2)

The system of claim 2, wherein the system bus includes a packet streaming interface link bus.

### Claim 4 (depends on 1)

The system of claim 1, further comprising an arbitrator coupled to the controller and configured to arbitrate among memory commands.

### Claim 5 (depends on 1)

The system of claim 1, further comprising a memory mapped register coupled to the controller and configured to receive a second memory command to perform a second memory operation.

### Claim 6 (depends on 5)

The system of claim 5, wherein the controller is configurable to:
receive a second event from the interface;
output the second memory command to perform the second memory operation in response the second event.

### Claim 7 (depends on 5)

The system of claim 5, further comprising a local bus coupled to the controller, wherein the controller is configurable to:
detect a second event on the local bus; and
output the second memory command to perform the second memory operation in response the second event.

### Claim 8 (depends on 1)

The system of claim 1, further comprising a configuration register coupled to the controller and configured to store an indication of the interface used to obtain the first memory command.

### Claim 9 (depends on 1)

The system of claim 1, further comprising a configuration register coupled to the controller and configured to store an indication of a queue to that the first memory command should be sent to.

### Claim 10 (depends on 1)

The system of claim 1, further comprising a bus coupled to the controller, wherein the controller is configurable to output a second event on the bus after the first memory command is triggered.

### Claim 11 (depends on 10)

The system of claim 10, further comprising a configuration register coupled to the controller and configured to store an indication of the second event to output on the bus after the first memory command is triggered.

### Claim 12 (depends on 1)

The system of claim 1, wherein the first memory command is a transfer command to move data from a source location to a destination location.

### Claim 13

A system comprising:
a system bus; and
a memory controller coupled to the system bus and including:
a local bus;
a buffer configured to store:
a first memory command to perform a first memory operation; and
a second memory command to perform a second memory operation,
wherein the memory controller is configurable to:
receive a first set of bits from the system bus;
detect a second set of bits on the local bus;
output the first memory command to perform the first memory operation in response to the first set of bits; and
output the second memory command to perform the second memory operation in response to the second set of bits.

### Claim 14 (depends on 13)

The system of claim 13, wherein the buffer is configured to receive the first memory command from the system bus.

### Claim 15 (depends on 13)

The system of claim 13,
wherein the memory controller includes a memory mapped register coupled to the buffer, and
wherein the buffer is configured to receive the second memory command from the memory mapped register.

### Claim 16 (depends on 15)

The system of claim 15, further comprising a processing core coupled to the memory mapped register and configurable to write the second memory command to the memory mapped register.

### Claim 17 (depends on 13)

The system of claim 13,
wherein the first memory command includes a virtual address, and
wherein the memory controller includes a memory management unit configured to translate the virtual address to a physical address.

### Claim 18 (depends on 13)

The system of claim 13, further comprising:
a power management controller coupled to the system bus; and
a security controller coupled to the system bus.

### Claim 19 (depends on 13)

The system of claim 13, wherein the first memory command is a transfer command to move data from a source location to a destination location.

### Claim 20 (depends on 13)

The system of claim 13, wherein the memory controller includes an arbitrator configured to arbitrate between the first memory command and the second memory command.