# US 2025/0093931 A1 · Autonomously managing core cluster frequencies using performance statistics in processor devices

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- Number: US 2025/0093931 A1
- Document ID: US20250093931A1
- Status: Published application
- Kind: A1
- Application number: 18/468,242
- Filed: 2023-09-15
- Published: 2025-03-20
- Earliest claimed: 2023-09-15
- Assignees: QUALCOMM Incorporated
- Applicants: QUALCOMM Incorporated
- Inventors: Mahadevamurty Nemani; Anubhav Mishra; Arun Sukheja; Nitin Makhija; Adarsh Baraka Ravi
- Web page: https://patentgrep.com/patent/US20250093931A1

## CPC

- G06F 1/28: Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
- G06F 1/324: by lowering clock frequency
- G06F 1/3243: {Power saving in microcontroller unit}
- G06F 1/3296: by lowering the supply or operating voltage
- G06F 9/44505: {Configuring for program initiating, e.g. using registry, configuration files}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

Autonomously managing core cluster frequencies using performance statistics in processor devices is disclosed herein. In some aspects, a cluster power management circuit of a processor device collects Activity Management Unit (AMU) statistics for multiple processor cores for each of one or more frequency operating points over a time interval. Based on the AMU statistics, the cluster power management circuit generates a performance model representing processor performance as a function of frequency, and uses the performance model and a power consumption measurement to generate an energy-per-instruction (EI) model representing energy per instruction as a function of frequency. The cluster power management circuit then generates an advantage model based on a first rate of change of the performance model as a function of frequency and a second rate of change of the EI model as a function of frequency, and identifies a target frequency operating point based on the advantage model.

## Claims

### Claim 1

A processor device comprising:
a core cluster comprising:
a plurality of processor cores comprising a corresponding plurality of Activity Management Units (AMUs);
a cluster power management circuit; and
a dynamic voltage and frequency scaling (DVFS) circuit; and
the cluster power management circuit configured to:
collect a plurality of AMU statistics from the plurality of AMUs for each frequency operating point of one or more frequency operating points over a time interval;
generate, based on the plurality of AMU statistics, a performance model representing processor performance as a function of frequency;
generate, based on the performance model and a power consumption measurement, an energy-per-instruction (EI) model representing energy per instruction as a function of frequency;
generate an advantage model based on a first rate of change of the performance model as a function of frequency and a second rate of change of the EI model as a function of frequency;
identify a target frequency operating point based on the advantage model; and
transmit the target frequency operating point to the DVFS circuit.

### Claim 2 (depends on 1)

The processor device of claim 1, wherein the DVFS circuit is configured to:
receive the target frequency operating point from the cluster power management circuit; and
set a frequency of the core cluster based on the target frequency operating point.

### Claim 3 (depends on 2)

The processor device of claim 2, wherein:
the target frequency operating point is higher than a current frequency of the core cluster; and
the DVFS circuit is configured to set the frequency of the core cluster based on the target frequency operating point by being configured to immediately raise the frequency of the core cluster.

### Claim 4 (depends on 2)

The processor device of claim 2, wherein:
the target frequency operating point is lower than a current frequency of the core cluster; and
the DVFS circuit is configured to set the frequency of the core cluster based on the target frequency operating point by being configured to incrementally lower the frequency of the core cluster.

### Claim 5 (depends on 1)

The processor device of claim 1, wherein the time interval comprises a programmable time interval.

### Claim 6 (depends on 1)

The processor device of claim 1, wherein the plurality of AMU statistics comprises one or more of a count of processor frequency cycles, a count of constant frequency cycles, a count of instructions retired, a count of front-end stalls, a count of memory stall cycles, a count of total demand misses of a last level cache (LLC), a count of front-end stalls that are memory-bound, a count of LLC demand accesses, a count of bus accesses, a count of bus access cycles, and a count of speculatively executed instructions.

### Claim 7 (depends on 1)

The processor device of claim 1, wherein the cluster power management circuit is configured to generate the performance model by being configured to calculate, for each frequency operating point of the one or more frequency operating points, a performance value comprising a product of the frequency operating point multiplied by an average number of instructions per clock cycle at the frequency operating point.

### Claim 8 (depends on 1)

The processor device of claim 1, wherein the cluster power management circuit is configured to generate the EI model by being configured to calculate, for each frequency operating point of the one or more frequency operating points, an EI value comprising a quotient of power consumption at the frequency operating point divided by a performance value for the frequency operating point.

### Claim 9 (depends on 1)

The processor device of claim 1, wherein the cluster power management circuit is configured to generate the advantage model by being configured to calculate the first rate of change of the performance model as a function of frequency divided by the second rate of change of the EI model as a function of frequency.

### Claim 10 (depends on 1)

The processor device of claim 1, wherein the cluster power management circuit is configured to identify the target frequency operating point based on the advantage model by being configured to determine a maximum frequency operating point that corresponds to an advantage value that is indicated by the advantage model as being greater than or equal to a threshold.

### Claim 11 (depends on 10)

The processor device of claim 10, wherein the threshold corresponds to a Quality of Service (QOS) hint provided by an operating system (OS) executed by the processor device.

### Claim 12 (depends on 10)

The processor device of claim 10, wherein the cluster power management circuit is configured to determine the maximum frequency operating point by being configured to determine the maximum frequency operating point as an interpolated value between an energy balanced frequency operating point and a performance frequency operating point, based on an energy performance preference (EPP) hint.

### Claim 13 (depends on 1)

The processor device of claim 1, integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter.

### Claim 14

A processor device, comprising:
means for collecting a plurality of Activity Management Unit (AMU) statistics from a plurality of AMUs, corresponding to a plurality of processor cores of a core cluster of the processor device, for each frequency operating point of one or more frequency operating points over a time interval;
means for generating, based on the plurality of AMU statistics, a performance model representing processor performance as a function of frequency;
means for generating, based on the performance model and a power consumption measurement, an energy-per-instruction (EI) model representing energy per instruction as a function of frequency;
means for generating an advantage model based on a first rate of change of the performance model as a function of frequency and a second rate of change of the EI model as a function of frequency;
means for identifying a target frequency operating point based on the advantage model; and
means for transmitting the target frequency operating point to a dynamic voltage and frequency scaling (DVFS) circuit of the processor device.

### Claim 15

A method for autonomously managing core cluster frequencies in processor-based devices, comprising:
collecting, by a cluster power management circuit of a processor device, a plurality of Activity Management Units (AMU) statistics from a plurality of AMUs, corresponding to a plurality of processor cores of a core cluster of the processor device, for each frequency operating point of one or more frequency operating points over a time interval;
generating, by the cluster power management circuit based on the plurality of AMU statistics, a performance model representing processor performance as a function of frequency;
generating, by the cluster power management circuit based on the performance model and a power consumption measurement, an energy-per-instruction (EI) model representing energy per instruction as a function of frequency;
generating, by the cluster power management circuit, an advantage model based on a first rate of change of the performance model as a function of frequency and a second rate of change of the EI model as a function of frequency;
identifying, by the cluster power management circuit, a target frequency operating point based on the advantage model; and
transmitting, by the cluster power management circuit, the target frequency operating point to a dynamic voltage and frequency scaling (DVFS) circuit of the processor device.

### Claim 16 (depends on 15)

The method of claim 15, further comprising:
receiving, by the DVFS circuit, the target frequency operating point from the cluster power management circuit; and
setting, by the DVFS circuit, a frequency of the core cluster based on the target frequency operating point.

### Claim 17 (depends on 16)

The method of claim 16, wherein:
the target frequency operating point is higher than a current frequency of the core cluster; and
setting the frequency of the core cluster based on the target frequency operating point comprises immediately raising the frequency of the core cluster.

### Claim 18 (depends on 16)

The method of claim 16, wherein:
the target frequency operating point is lower than a current frequency of the core cluster; and
setting the frequency of the core cluster based on the target frequency operating point comprises incrementally lowering the frequency of the core cluster.

### Claim 19 (depends on 15)

The method of claim 15, wherein the time interval comprises a programmable time interval.

### Claim 20 (depends on 15)

The method of claim 15, wherein the plurality of AMU statistics comprises one or more of a count of processor frequency cycles, a count of constant frequency cycles, a count of instructions retired, a count of front-end stalls, a count of memory stall cycles, a count of total demand misses of a last level cache (LLC), a count of front-end stalls that are memory-bound, a count of LLC demand accesses, a count of bus accesses, a count of bus access cycles, and a count of speculatively executed instructions.

### Claim 21 (depends on 15)

The method of claim 15, wherein generating the performance model comprises calculating, for each frequency operating point of the one or more frequency operating points, a performance value comprising a product of the frequency operating point multiplied by an average number of instructions per clock cycle at the frequency operating point.

### Claim 22 (depends on 15)

The method of claim 15, wherein generating the EI model comprises calculating, for each frequency operating point of the one or more frequency operating points, an EI value comprising a quotient of power consumption at the frequency operating point divided by a performance value for the frequency operating point.

### Claim 23 (depends on 15)

The method of claim 15, wherein generating the advantage model comprises calculating the first rate of change of the performance model as a function of frequency divided by the second rate of change of the EI model as a function of frequency.

### Claim 24 (depends on 15)

The method of claim 15, wherein identifying the target frequency operating point based on the advantage model comprises determining a maximum frequency operating point that corresponds to an advantage value that is indicated by the advantage model as being greater than or equal to a threshold.

### Claim 25 (depends on 24)

The method of claim 24, wherein the threshold corresponds to a Quality of Service (QoS) hint provided by an operating system (OS) executed by the processor device.

### Claim 26 (depends on 24)

The method of claim 24, wherein determining the maximum frequency operating point comprises determining the maximum frequency operating point as an interpolated value between an energy balanced frequency operating point and a performance frequency operating point, based on an energy performance preference (EPP) hint.

### Claim 27

A non-transitory computer-readable medium, having stored thereon computer-executable instructions that, when executed, cause a processor device of a processor-based device to:
collect a plurality of Activity Management Units (AMU) statistics from a plurality of AMUs, corresponding to a plurality of processor cores of a core cluster of the processor device, for each frequency operating point of one or more frequency operating points over a time interval;
generate, based on the plurality of AMU statistics, a performance model representing processor performance as a function of frequency;
generate, based on the performance model and a power consumption measurement, an energy-per-instruction (EI) model representing energy per instruction as a function of frequency;
generate an advantage model based on a first rate of change of the performance model as a function of frequency and a second rate of change of the EI model as a function of frequency;
identify a target frequency operating point based on the advantage model; and
transmit the target frequency operating point to a dynamic voltage and frequency scaling (DVFS) circuit of the processor device.

### Claim 28 (depends on 27)

The non-transitory computer-readable medium of claim 27, wherein the computer-executable instructions further cause the processor device to:
receive the target frequency operating point; and
set a frequency of the core cluster based on the target frequency operating point.

### Claim 29 (depends on 28)

The non-transitory computer-readable medium of claim 28, wherein:
the target frequency operating point is higher than a current frequency of the core cluster; and
the computer-executable instructions cause the processor device to set the frequency of the core cluster based on the target frequency operating point by causing the processor device to immediately raise the frequency of the core cluster.

### Claim 30 (depends on 28)

The non-transitory computer-readable medium of claim 28, wherein:
the target frequency operating point is lower than a current frequency of the core cluster; and
the computer-executable instructions cause the processor device to set the frequency of the core cluster based on the target frequency operating point by causing the processor device to incrementally lower the frequency of the core cluster.

### Claim 31 (depends on 27)

The non-transitory computer-readable medium of claim 27, wherein the time interval comprises a programmable time interval.

### Claim 32 (depends on 27)

The non-transitory computer-readable medium of claim 27, wherein the plurality of AMU statistics comprises one or more of a count of processor frequency cycles, a count of constant frequency cycles, a count of instructions retired, a count of front-end stalls, a count of memory stall cycles, a count of total demand misses of a last level cache (LLC), a count of front-end stalls that are memory-bound, a count of LLC demand accesses, a count of bus accesses, a count of bus access cycles, and a count of speculatively executed instructions.

### Claim 33 (depends on 27)

The non-transitory computer-readable medium of claim 27, wherein the computer-executable instructions cause the processor device to generate the performance model by causing the processor device to calculate, for each frequency operating point of the one or more frequency operating points, a performance value comprising a product of the frequency operating point multiplied by an average number of instructions per clock cycle at the frequency operating point.

### Claim 34 (depends on 27)

The non-transitory computer-readable medium of claim 27, wherein the computer-executable instructions cause the processor device to generate the EI model by causing the processor device to calculate, for each frequency operating point of the one or more frequency operating points, an EI value comprising a quotient of power consumption at the frequency operating point divided by a performance value for the frequency operating point.

### Claim 35 (depends on 27)

The non-transitory computer-readable medium of claim 27, wherein the computer-executable instructions cause the processor device to generate the advantage model by causing the processor device to calculate the first rate of change of the performance model as a function of frequency divided by the second rate of change of the EI model as a function of frequency.

### Claim 36 (depends on 27)

The non-transitory computer-readable medium of claim 27, wherein the computer-executable instructions cause the processor device to identify the target frequency operating point based on the advantage model by causing the processor device to determine a maximum frequency operating point that corresponds to an advantage value that is indicated by the advantage model as being greater than or equal to a threshold.

### Claim 37 (depends on 36)

The non-transitory computer-readable medium of claim 36, wherein the threshold corresponds to a Quality of Service (QOS) hint provided by an operating system (OS) executed by the processor device.

### Claim 38 (depends on 36)

The non-transitory computer-readable medium of claim 36, wherein the computer-executable instructions cause the processor device to determine the maximum frequency operating point by causing the processor device to determine the maximum frequency operating point as an interpolated value between an energy balanced frequency operating point and a performance frequency operating point, based on an energy performance preference (EPP) hint.