# US 2025/0093901 A1 · Buffer circuit for capacitive loads > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2025/0093901 A1 - Document ID: US20250093901A1 - Status: Published application - Kind: A1 - Application number: 18/470,626 - Filed: 2023-09-20 - Published: 2025-03-20 - Earliest claimed: 2023-09-20 - Assignees: Semiconductor Components Industries, LLC - Applicants: Semiconductor Components Industries, LLC - Inventors: Shiva Shanthan VELURI; Anirudh OBEROI - Web page: https://patentgrep.com/patent/US20250093901A1 ## CPC - G05F 3/262: {using field-effect transistors only} - G05F 1/575: characterised by the feedback circuit - H03F 3/45475: {using IC blocks as the active amplifying circuit} - G05F: SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES - H03F: AMPLIFIERS ## Abstract A reference buffer circuit for buffering a reference voltage is disclosed. The reference buffer circuit includes an input circuit that may generate a replica of the reference voltage. A feedback circuit may generate a charging current using a current mirror circuit and a bias current. A value of the charging current may be greater than a value of the bias current. The feedback circuit may provide a buffered version of the reference voltage at a reference node using the charging current and the replica voltage. An output stage circuit may sink a compensation current from the reference node. ## Claims ### Claim 1 An apparatus, comprising: an input circuit configured to generate a replica voltage using a reference voltage, wherein the replica voltage is offset from the reference voltage; a feedback circuit configured to: generate a bias current; generate a charging current using the bias current, wherein a value of the charging current is greater than a value of the bias current; and provide a buffered reference voltage at a reference node using the charging current and the replica voltage; and an output stage circuit configured to sink, based on the buffered reference voltage, a compensation current from the reference node. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein to provide the buffered reference voltage, the feedback circuit is further configured to: source the charging current to the reference node; and sink a portion of the charging current from the reference node, wherein a value of the portion of the charging current is based on the replica voltage. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein the feedback circuit includes a current mirror circuit that includes a diode-connected transistor and a mirror transistor coupled between a power supply node and the reference node, wherein a first beta ratio of the diode-connected transistor is less than a second beta ratio of the mirror transistor, and wherein the mirror transistor is configured to source the charging current to the reference node based on a current flowing in the diode-connected transistor. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein the output stage circuit includes a transistor coupled between the reference node and a ground supply node, wherein the transistor is configured to adjust a conductance between the reference node and the ground supply node based on the buffered reference voltage and the replica voltage. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein the output stage circuit includes a transistor coupled between the reference node and a ground supply node, and wherein the output stage circuit is further configured to: generate an adjustment current using the bias current, wherein a value of the adjustment current is less than the value of the bias current; and modify a voltage level of a control terminal of the transistor using the adjustment current. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein the replica voltage is less than the reference voltage and wherein to generate the replica voltage, the input circuit is further configured to: convert the reference voltage to a first current; generate a second current using a bias voltage; and combine the first current and the second current to generate the replica voltage. ### Claim 7 A method, comprising: receiving, by a buffer circuit, a reference voltage; generating, by the buffer circuit, a replica voltage using the reference voltage, wherein the replica voltage is offset from the reference voltage; generating, by the buffer circuit, a bias current; generating, by the buffer circuit, a charging current using the bias current, wherein the charging current is greater than the bias current; and providing, by the buffer circuit, a buffered reference voltage at a reference node using the charging current and the replica voltage. ### Claim 8 (depends on 7) The method of claim 7, wherein providing the buffered reference voltage includes: sourcing the charging current to the reference node; and sinking a portion of the charging current from the reference node, wherein a value of the portion of the charging current is based on the replica voltage. ### Claim 9 (depends on 7) The method of claim 7, wherein the buffer circuit includes an output stage circuit and, further comprising sinking, by the output stage circuit, a compensation current from the reference node. ### Claim 10 (depends on 9) The method of claim 9, wherein the output stage circuit includes a transistor coupled between the reference node and a ground supply node, and wherein sinking the compensation current includes adjusting, by the transistor, a conductance between the reference node and the ground supply node based on a value of the replica voltage. ### Claim 11 (depends on 9) The method of claim 9, wherein the output stage circuit includes a transistor coupled between the reference node and a ground supply node, and further comprising: generating, by the output stage circuit, an adjustment current using the bias current, wherein a value of the adjustment current is less than a value of the bias current; and modifying, by the transistor, a conductance between the reference node and the ground supply node using the adjustment current. ### Claim 12 (depends on 11) The method of claim 11, further comprising disabling the output stage circuit by coupling a control terminal of the transistor to a power supply node. ### Claim 13 (depends on 7) The method of claim 7, wherein generating the replica voltage includes: converting the reference voltage to a first current; generating a second current using a bias voltage; and combining the first current and the second current to generate the replica voltage. ### Claim 14 A system, comprising: an image sensor circuit coupled to a reference node; and a reference buffer circuit configured to: receive a reference voltage; generate a bias current; generate a charging current using the bias current; and provide a buffered reference voltage at the reference node based on the reference voltage and using the charging current. ### Claim 15 (depends on 14) The system of claim 14, wherein to provide the buffered reference voltage, the reference buffer circuit is further configured to: generate a replica voltage using the reference voltage, wherein the replica voltage is offset from the reference voltage; source the charging current to the reference node; and sink a portion of the charging current from the reference node, wherein a value of the portion of the charging current is based on the replica voltage. ### Claim 16 (depends on 15) The system of claim 15, wherein the reference buffer circuit is further configured to sink a compensation current from the reference node. ### Claim 17 (depends on 16) The system of claim 16, wherein to sink the compensation current from the reference node, the reference buffer circuit is further configured to adjust a conductance between the reference node and a ground supply node based on a value of the replica voltage and the buffered reference voltage. ### Claim 18 (depends on 16) The system of claim 16, wherein to sink the compensation current from the reference node, the reference buffer circuit is further configured to: generate an adjustment current using the bias current, wherein a value of the adjustment current is less than the bias current; and modify a conductance between the reference node and a ground supply node using the adjustment current and the buffered reference voltage. ### Claim 19 (depends on 16) The system of claim 16, wherein to generate the replica voltage, the reference buffer circuit is further configured to: convert the reference voltage to a first current; generate a second current using a bias voltage; and combine the first current and the second current to generate the replica voltage. ### Claim 20 (depends on 14) The system of claim 14, wherein the image sensor circuit is further configured to charge at least one capacitor using the buffered reference voltage.