Controller for an electronically controlled resistor

A controller 220 for an electronically controlled resistor (ECR) 222, comprising:

• a first operational amplifier 208,
• a reference resistor Rref,
• a constant voltage source 214,
• a bias resistor Rbias,
• an adder 206,
• a controllable current generator 212,
• a first terminal 1 of said controller 220 for connecting to a first terminal of an external variable control resistor Rc,
• a second terminal 2 of said controller 220 for receiving a feedback signal from a common node of an external sense resistor Rsense and an external active element 224,
• a third terminal 3 of said controller 220 for connecting to a control terminal of the external active element 224,
• a fourth terminal 4 of said controller 220 for connecting to a second terminal of the external variable control resistor Rc,
• a fifth terminal 5 of said controller 220 for connecting to a low-potential terminal 12 of the ECR 222,
• a sixth terminal 6 of said controller 220 for connecting to a high-potential terminal 10 of the ECR 222,
• the fourth terminal 4 and the fifth terminal 5 of the controller 220 being connected to each other,
• an output of the first operational amplifier 208 being connected to the third terminal 3 of said controller 220,
• a first terminal of the reference resistor Rref being connected to a non-inverting input of the first operational amplifier 208 and
• a second terminal of the reference resistor Rref being connected to the fifth terminal 5 of said controller 220,
• a first terminal of the bias resistor Rbias, being connected to the sixth terminal 6 of said controller 220
• a second terminal of the bias resistor Rbias, being connected to the non-inverting input of the first operational amplifier 208,
• a first input of the adder 206 being connected to the first terminal 1 of said controller 220,
• a second input of the adder 206 being connected to the second terminal 2 of said controller 220,
• an output of the adder 206 beings connected to an inverting input of the first operational amplifier 208,
• the controllable current generator 212 comprising a second operational amplifier 302, a third operational amplifier 303, a first transistor 311, a second transistor 312, a first resistor Rcg1, a second resistor Rcg2, and a third resistor Rcg3, a control input 24 of the controllable current generator 212 being connected to the second 2 terminal of the controller 220 and to a non-inverting input of the second operational amplifier 302, an inverting input of the second operational amplifier 302 being connected to a common node of the first transistor 311 and the first resistor Rcg1 connected in series, an output of the second operational amplifier 302 being connected to a gate of the first transistor 311, an output 26 of the controllable current generator 212 being connected to the first terminal 1 of said controller 220, to the inverting input of the first operational amplifier 208 and to the second transistor 312, an output of the third operational amplifier 303 being connected to a gate of the second transistor 312, a non-inverting input of the third operational amplifier 303 being connected to a common node of the first transistor 311 and the second resistor Rcg2 connected in series, an inverting input of the third operational amplifier 303 being connected to a common node of the second transistor 312 and the third resistor Rcg3 connected in series, a common node of the second Rcg2 and third Rcg3 resistors being connected to a terminal 22 of the controllable current generator 212 for connecting to the constant voltage source 214 to power the controllable current generator.

An integrated circuit (IC) for a controller 220 for an ECR 222, the IC comprising:

• a first operational amplifier 208,
• a reference resistor Rref,
• a bias resistor Rbias,
• a first terminal 1 designed for connecting to a first terminal of an external variable control resistor Rc,
• a second terminal 2 designed for receiving a feedback signal from a common node of an external sense resistor Rsense and an external active element 224,
• a third terminal 3 designed for connecting to a control terminal of the external active element 224,
• a fourth terminal 4 designed for connecting to a second terminal of the external variable control resistor Rc,
• a fifth terminal 5 designed for connecting to a low-potential terminal 12 of the ECR 222,
• a sixth terminal 6 designed for connecting to a high-potential terminal 10 of the ECR 222, and
• a controllable current generator 212,
• the controllable current generator 212 comprising a second operational amplifier 302, a third operational amplifier 303, a first transistor 311, a second transistor 312, a first resistor Rcg1, a second resistor Rcg2, and a third resistor Rcg3, a control input 24 of the controllable current generator 212 being designed for connecting to the second terminal 2 and to a non-inverting input of the second operational amplifier 302, an inverting input of the second operational amplifier 302 being connected to a common node of the first transistor 311 and the first resistor Rcg1 connected in series, an output of the second operational amplifier 302 being connected to a gate of the first transistor 311, an output 26 of the controllable current generator 212 being designed for connecting to the first terminal 1, to the inverting input of the first operational amplifier 208 and to the second transistor 312, the output of the third operational amplifier 303 is connected to the gate of the second transistor 312, a non-inverting input of the third operational amplifier 303 being connected to a common node of the first transistor 311 and the second resistor Rcg2 connected in series, an inverting input of the third operational amplifier 303 beings connected to a common node of the second transistor 312 and the third resistor Rcg3 connected in series,
• the output of the first operational amplifier 208 being connected to the third terminal 3,
• a first terminal of the reference resistor Rref being connected to the non-inverting input of the first operational amplifier 208,
• a second terminal of the reference resistor Rref being connected to the fifth terminal 5,
• a first terminal of the bias resistor Rbias being connected to the sixth terminal 6,
• a second terminal of the bias resistor Rbias being connected to the non-inverting input of the first operational amplifier 208, and
• the fourth terminal 4 and the fifth terminal 5 being connected with each other.