# US 2025/0093409 A1 · Built-in self test with current measurement for analog circuit verification

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- Number: US 2025/0093409 A1
- Document ID: US20250093409A1
- Status: Published application
- Kind: A1
- Application number: 18/468,456
- Filed: 2023-09-15
- Published: 2025-03-20
- Earliest claimed: 2023-09-15
- Assignees: Semiconductor Components Industries, LLC
- Applicants: Semiconductor Components Industries, LLC
- Inventors: Francois LAULANET; Jorg Jos DANIELS
- Web page: https://patentgrep.com/patent/US20250093409A1

## CPC

- G01R 31/2884: {using dedicated test connectors, test elements or test circuits on the IC under test (G01R31/2855 takes precedence)}
- G01R 31/2894: {Aspects of quality control [QC] (G01R31/31718 takes precedence; program control for QC G05B19/41875)}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

Illustrative integrated circuit devices are provided with built-in self test circuit designs and verification methods. One disclosed integrated circuit device includes: an analog circuit block configured to be powered by a current flow from a first power rail and an intermediate node; a current sensor configured to provide digital measurements of the current flow; a built-in self test circuit configured to set the analog circuit block in a sequence of operating modes and coupled to the current sensor to capture for each operating mode a corresponding one of the digital measurements.

## Claims

### Claim 1

An integrated circuit device that comprises:
an analog circuit block configured to be powered by a current flow between a first power rail and an intermediate node;
a current sensor configured to provide digital measurements of the current flow; and
a built-in self test circuit configured to set the analog circuit block in an operating mode from a sequence of operating modes and coupled to the current sensor to capture for each operating mode in the sequence a corresponding one of the digital measurements.

### Claim 2 (depends on 1)

The integrated circuit device of claim 1, wherein the current sensor includes:
a resistor bank that couples the intermediate node to a second power rail and configured to convert the current flow into a voltage drop;
a comparator configured to provide an output indicating whether the voltage drop exceeds a fixed reference voltage; and
a controller configured to iteratively adjust the resistor bank based on the output of the comparator to provide the digital measurements of current flow.

### Claim 3 (depends on 1)

The integrated circuit device of claim 1, wherein the analog circuit block is one of multiple analog circuit blocks each having a corresponding sequence of operating modes to be set by the built-in self test circuit, each of the multiple analog circuit blocks configured to be powered by current flow from the first power rail to the intermediate node.

### Claim 4 (depends on 3)

The integrated circuit device of claim 3, wherein the built-in self test circuit is configured to capture the digital measurements for a given one of the multiple analog circuit blocks while disabling all other ones of the multiple analog circuit blocks.

### Claim 5 (depends on 1)

The integrated circuit device of claim 1, wherein the sequence of operating modes is specified by a test pattern input to the built-in self test circuit.

### Claim 6 (depends on 5)

The integrated circuit device of claim 5, wherein the built-in self test circuit is configured to output a device signature including the digital measurements.

### Claim 7 (depends on 6)

The integrated circuit device of claim 6, wherein the built-in self test circuit includes memory configured to store the test pattern and the digital measurements.

### Claim 8 (depends on 7)

The integrated circuit device of claim 7, wherein the built-in self test circuit includes a sequencer configured to iterate through the sequence of operating modes for the analog circuit block and to store the corresponding one of the digital measurements in the memory.

### Claim 9

A method that comprises testing multiple integrated circuit devices from a given manufacturing batch, the testing including, for each of the multiple integrated circuit devices:
powering an analog circuit block with a current flow from a first power rail;
iterating through a sequence of operating modes for the analog circuit block;
for each operating mode in the sequence, storing a digital measurement of the current flow corresponding to that operating mode;
transferring a device signature that includes the stored digital measurements to an external tester; and
failing the integrated circuit device if the device signature is not consistent with device signatures of other ones of the multiple integrated circuit devices.

### Claim 10 (depends on 9)

The method of claim 9, wherein the given manufacturing batch comprises the multiple integrated circuit devices patterned on a given wafer.

### Claim 11 (depends on 9)

The method of claim 9, further comprising obtaining the digital measurements by:
comparing a reference voltage to a voltage drop from a resistor bank that couples an intermediate node to a second power rail; and
iteratively adjusting the resistor bank based on said comparing.

### Claim 12 (depends on 9)

The method of claim 9, wherein the analog circuit block is one of multiple analog circuit blocks in the integrated circuit device, and wherein the method further includes importing a test pattern that specifies for each analog circuit block in the multiple analog circuit blocks a corresponding sequence of operating modes.

### Claim 13 (depends on 12)

The method of claim 12, wherein the method includes disabling the other ones of the multiple analog circuit blocks during said iterating through the sequence of operating modes for the analog circuit block.

### Claim 14 (depends on 13)

The method of claim 13, wherein said transferring includes communicating the device signature to the external tester via a serial test bus.

### Claim 15 (depends on 9)

The method of claim 9, wherein the device signature is determined to be not consistent if a maximum absolute difference between corresponding digital measurements of different integrated circuit devices falls below a predetermined threshold.

### Claim 16

An integrated circuit device that comprises:
multiple analog circuit blocks each coupled between a first power rail and an intermediate power node;
a current sensor coupled between the intermediate power node and a second power rail, the current sensor configured to provide digital measurements of current flow between the intermediate power node and the second power rail; and
a sequencer configured to iterate through the multiple analog circuit blocks, enabling one at a time pursuant to a test pattern, the test pattern further specifying a sequence of operating modes for the enabled analog circuit block, and the sequencer further configured to capture a digital measurement of the current flow for each operating mode of each analog circuit block.

### Claim 17 (depends on 16)

The integrated circuit device of claim 16, wherein the current sensor includes:
a resistor bank that couples the intermediate node to the second power rail and configured to convert the current flow into a voltage drop;
a comparator configured to compare the voltage drop to a fixed reference voltage; and
a controller configured to adjust the resistor bank as needed for the voltage drop to converge to the fixed reference voltage.

### Claim 18 (depends on 17)

The integrated circuit device of claim 17, further comprising a bypass switch for the resistor bank configured to disable the current sensor when closed.

### Claim 19 (depends on 16)

The integrated circuit device of claim 16, further comprising:
a memory; and
a built-in self test interface coupled to the memory to store the test pattern and to output a device signature that includes the digital measurements for each operating mode of each analog circuit block.

### Claim 20 (depends on 17)

The integrated circuit device of claim 17, wherein the controller is configured to adjust the resistor bank in accordance with a binary search.