Low latency, low loss, scalable throughput support and queuing

A system comprising:

• a memory storage;
• and
• a processing unit coupled to the memory storage, wherein the processing unit is operative to:
• determine a flow for a Low Latency, Low Loss, Scalable Throughput (L4S) capable Station (STA) is L4S enabled;
• implement a shallow queuing mechanism for queuing traffic by replacing one or more alternate queues with one or more L4S queues, the shallow queuing mechanism comprising one or more classic queues and the one or more L4S queues;
• and
• queue L4S traffic of the flow in at least one of the one or more L4S queues.

A non-transitory computer-readable medium that stores a set of instructions which when executed perform a method executed by the set of instructions comprising:

• determining a flow for a Low Latency, Low Loss, Scalable Throughput (L4S) capable Station (STA) is L4S enabled;
• in response to determining the flow is L4S enabled, implementing a shallow queuing mechanism for queuing traffic by replacing one or more alternate queues with one or more L4S queues, the shallow queuing mechanism comprising one or more classic queues and the one or more L4S queues;
• and
• queuing L4S traffic of the flow in at least one of the one or more L4S queues.