Signal drop compensated memory

An apparatus, comprising:

• a memory array comprising memory cells;
• sensing circuitry coupled to the memory array and comprising:
• a decoder coupled to the memory array;
• circuitry, which replicates the decoder, coupled to the memory array;
• and
• different circuitry coupled to the circuitry and to the memory array, wherein the different circuitry is configured to provide a signal to a terminal of a selected transistor, using a first transistor and a capacitor, and a mirrored signal to the circuitry using a second transistor and the capacitor, wherein the capacitor is coupled to a first gate of the first transistor and a second gate of the second transistor;
• wherein the circuitry is configured to provide a different signal corresponding to a signal drop of the circuitry to a gate of the selected transistor, wherein the signal drop replicates a corresponding signal drop of the decoder;
• wherein the sensing circuitry is configured to:
• provide a sensing signal to the gate of the selected transistor simultaneously with the different signal;
• and
• sense a state of the selected transistor.

A method, comprising:

• providing, from a current mirror and using the capacitor, a first transistor coupled to the capacitor via a first gate of the first transistor, and a second transistor coupled to the capacitor via a second gate of the second transistor, a mirrored signal to a terminal of a selected transistor and to circuitry subsequent to providing a signal to the terminal of the selected transistor of sensing circuitry;
• generating a signal drop, at the circuitry, using the mirrored signal received from the second transistor, wherein the signal drop replicates a corresponding signal drop of a decoder;
• and
• responsive to determining that the signal drop is greater than a threshold, setting a register to identify a plurality of actions that are to be performed on an output of the decoder comprising the selected transistor.