# US 2025/0086102 A1 · Processing Memory Access Transactions > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2025/0086102 A1 - Document ID: US20250086102A1 - Status: Published application - Kind: A1 - Application number: 18/791,035 - Filed: 2024-07-31 - Published: 2025-03-13 - Earliest claimed: 2023-08-04 - Applicants: Imagination Technologies Limited - Inventors: Peter Vrabel; Jack Andrew; Ravindranath Ramalingaiah Mannan - Web page: https://patentgrep.com/patent/US20250086102A1 ## CPC - G06F 12/0223: {User address space allocation, e.g. contiguous or non contiguous base addressing} - G06F 13/1626: {by reordering requests} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A memory attribute structure comprises one or more memory address entries. Each memory address entry comprising a respective memory address range mapped to a respective priority level. The memory attribute table is used when processing a memory access transaction through an execution path of a processing system. During said processing, a memory address of the memory access transaction is determined. The memory attribute structure is used to determine a priority level mapped to the determined memory address, and the memory access transaction is processed based on the determined priority level. ## Claims ### Claim 1 A method of processing a memory access transaction through an execution path of a processing system, wherein a memory attribute structure comprises one or more memory address entries, each memory address entry comprising a respective memory address range mapped to a respective priority level of a set of priority levels, the method comprising: determining a memory address of the memory access transaction; using the memory attribute structure to determine a priority level mapped to the determined memory address; and processing the memory access transaction based on the determined priority level. ### Claim 2 (depends on 1) The method of claim 1, wherein processing the memory access transaction comprises: associating the memory access transaction with the determined priority level; and prioritising the memory access transaction over one or more respective memory access transactions associated with respective priority levels having a lower priority than the determined priority level. ### Claim 3 (depends on 2) The method of claim 2, wherein said prioritising comprises prioritising selection of the memory access transaction for transmission over one or more interfaces of the processing system. ### Claim 4 (depends on 3) The method of claim 3, wherein the one or more interfaces comprise a CPU-to-interconnect interface and/or an interconnect-to-slave interface. ### Claim 5 (depends on 2) The method of claim 2, wherein said prioritising comprises prioritising acceptance of the memory transaction into buffer space. ### Claim 6 (depends on 2) The method of claim 2, wherein said prioritising comprises prioritising processing of the memory access transaction by one or more components of the execution path. ### Claim 7 (depends on 2) The method of claim 2, wherein said associating comprises associating a flag with the memory access transaction, wherein the flag indicates the priority level. ### Claim 8 (depends on 2) The method of claim 2, wherein the memory access transaction is not prioritised over one or more respective memory access transactions associated with respective priority levels having a higher priority than the determined priority level. ### Claim 9 (depends on 1) The method of claim 1, wherein the processing system comprises one or more buffer spaces reserved for use by memory access transactions associated with a predetermined priority level, and wherein processing the memory access transaction comprises allocating the memory access transaction to one of said reserved buffer spaces. ### Claim 10 (depends on 9) The method of claim 9, wherein multiple reserved buffer spaces are reserved for memory access transactions associated with the determined priority level. ### Claim 11 (depends on 9) The method of claim 9, wherein the processing system comprises a plurality of buffer spaces, and wherein the method comprises marking one or more of the plurality of buffers spaces as the one or more reserved buffer spaces ### Claim 12 (depends on 9) The method of claim 9, wherein the memory attribute structure comprises, for each respective priority level of the set of priority levels, a respective indication of one or more respective reserved buffer spaces. ### Claim 13 (depends on 1) The method of claim 1, wherein the memory attribute structure is configurable by a user of the processing system. ### Claim 14 (depends on 13) The method of claim 13, wherein the respective priority level mapped to the respective memory address range is configurable. ### Claim 15 (depends on 9) The method of claim 9, wherein the memory attribute structure is configurable by a user of the processing system, and wherein the one or more reserved buffer spaces reserved for use by memory access transactions associated with a respective priority level is configurable. ### Claim 16 (depends on 13) The method of claim 13, wherein a number of priority levels of the set of priority levels is configurable. ### Claim 17 (depends on 1) The method of claim 1, wherein the memory attribute structure is configurable by a user of the processing system, and wherein a respective number of reserved buffer spaces per respective priority level is configurable. ### Claim 18 (depends on 13) The method of claim 13, wherein the memory attribute structure is configurable at build time of the processing system. ### Claim 19 A non-transitory computer-readable storage medium having computer code stored thereon, which when run on a processing system, causes the processing system to process a memory access transaction through an execution path of the processing system, wherein a memory attribute structure comprises one or more memory address entries, each memory address entry comprising a respective memory address range mapped to a respective priority level of a set of priority levels, and wherein said processing a memory access transaction comprises: determining a memory address of the memory access transaction; using the memory attribute structure to determine a priority level mapped to the determined memory address; and processing the memory access transaction based on the determined priority level. ### Claim 20 A processing system for processing a memory access transaction through an execution path of the processing system, wherein the processing system has stored, in memory, a memory attribute structure comprising one or more memory address entries, each memory address entry comprising a respective memory address range mapped to a respective priority level of a set of priority levels, the processing system being configured to: determine a memory address of the memory access transaction; use the memory attribute structure to determine a priority level mapped to the determined memory address; and process the memory access transaction based on the determined priority level.