# US 2025/0085343 A1 · Commanded jtag test access port operations

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- Number: US 2025/0085343 A1
- Document ID: US20250085343A1
- Status: Published application
- Kind: A1
- Application number: 18/956,830
- Filed: 2024-11-22
- Published: 2025-03-13
- Earliest claimed: 2010-03-10
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Lee D. Whetsel
- Web page: https://patentgrep.com/patent/US20250085343A1

## CPC

- G01R 31/3177: Testing of logic operation, e.g. by logic analysers
- G01R 31/318533: {using scanning techniques, e.g. LSSD, Boundary Scan, JTAG}
- G01R 31/318552: {Clock circuits details}
- G01R 31/318572: {Input/Output interfaces}
- G01R 31/318597: {JTAG or boundary scan test of memory devices (other scan testing of memories G11C29/32)}
- G06F 9/30098: {Register arrangements}
- G06F 11/348: {Circuit details, i.e. tracer hardware}
- G06F 11/3656: {using a specific debug interface}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

The disclosure describes a novel method and apparatus for improving the operation of a TAP architecture in a device through the use of Command signal inputs to the TAP architecture. In response to a Command signal input, the TAP architecture can perform streamlined and uninterrupted Update, Capture and Shift operation cycles to a target circuit in the device or streamlined and uninterrupted capture and shift operation cycles to a target circuit in the device. The Command signals can be input to the TAP architecture via the devices dedicated TMS or TDI inputs or via a separate CMD input to the device.

## Claims

### Claim 1

A device comprising:
a test clock (TCK) input;
a test mode select (TMS) input;
a test data in (TDI) input;
a test data out (TDO) output;
an instruction register coupled to the TDI input and to the TDO output;
a command circuit coupled to the TCK input and to the TMS input;
a first routing circuit coupled to the instruction register and to the command circuit; and
a first data register coupled to the first routing circuit.

### Claim 2 (depends on 1)

The device of claim 1, further comprising:
a second routing circuit coupled to the instruction register and to the command circuit; and
a second data register coupled to the second routing circuit.

### Claim 3 (depends on 1)

The device of claim 1, further comprising a state machine coupled to the TCK input, the TMS input, and the command circuit.

### Claim 4 (depends on 3)

The device of claim 3, wherein the state machine is coupled to the instruction register and to the first routing circuit.

### Claim 5 (depends on 1)

The device of claim 1, wherein the command circuit is configurable to:
receive a signal from the TMS input;
initiate a first action in response to receiving the signal at a first clock edge of the TCK input; and
initiate a second action according to IEEE 1149.1 in response to receiving the signal at a second clock edge of the TCK input,
wherein the first clock edge is opposite the second clock edge.

### Claim 6 (depends on 5)

The device of claim 5, wherein to initiate the first action, the command circuit is configurable to initiate a debug operation in response to receiving the signal.

### Claim 7 (depends on 5)

The device of claim 5, wherein to initiate the first action, the command circuit is configurable to initiate an update operation in response to receiving the signal.

### Claim 8 (depends on 7)

The device of claim 7, wherein to initiate the first action, the command circuit is configurable to initiate a capture operation after the update operation.

### Claim 9 (depends on 8)

The device of claim 8, wherein to initiate the first action, the command circuit is configurable to initiate a shift operation after the capture operation.

### Claim 10 (depends on 1)

The device of claim 1, further comprising a test compression architecture including the first data register.

### Claim 11

A system comprising:
a daisy chain of devices including a first device and a second device;
a clock input coupled to the first device and to the second device;
a test clock (TCK) input coupled to the first device and to the second device;
a test mode select (TMS) input coupled to the first device and to the second device;
wherein the first device includes:
an instruction register;
a command circuit coupled to the TCK input and to the TMS input;
a first routing circuit coupled to the instruction register and to the command circuit; and
a first data register coupled to the first routing circuit.

### Claim 12 (depends on 11)

The system of claim 11,
wherein the first device includes a test data out (TDO) output coupled to the instruction register, and
wherein the second device includes a test data in (TDI) input coupled to the TDO output of the first device.

### Claim 13 (depends on 11)

The system of claim 11, wherein the first device includes:
a second routing circuit coupled to the instruction register and to the command circuit; and
a second data register coupled to the second routing circuit.

### Claim 14 (depends on 11)

The system of claim 11, wherein the first device includes a state machine coupled to the TCK input, the TMS input, and the command circuit.

### Claim 15 (depends on 14)

The system of claim 14, wherein the state machine is coupled to the instruction register and to the first routing circuit.

### Claim 16 (depends on 11)

The system of claim 11, wherein the command circuit is configurable to:
receive a signal from the TMS input;
initiate a first action in response to receiving the signal at a first clock edge of the TCK input; and
initiate a second action according to IEEE 1149.1 in response to receiving the signal at a second clock edge of the TCK input,
wherein the first clock edge is opposite the second clock edge.

### Claim 17 (depends on 16)

The system of claim 16, wherein to initiate the first action, the command circuit is configurable to initiate a debug operation in response to receiving the signal.

### Claim 18 (depends on 16)

The system of claim 16, wherein to initiate the first action, the command circuit is configurable to:
initiate an update operation in response to receiving the signal; and
initiate a capture operation after the update operation.

### Claim 19 (depends on 18)

The system of claim 18, wherein to initiate the first action, the command circuit is configurable to initiate a shift operation after the capture operation.

### Claim 20 (depends on 11)

The system of claim 11, further comprising a test compression architecture including the first data register.