# US 2025/0085341 A1 · Systems and methods for isolating faults in die-to-die interconnects > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2025/0085341 A1 - Document ID: US20250085341A1 - Status: Published application - Kind: A1 - Application number: 18/464,529 - Filed: 2023-09-11 - Published: 2025-03-13 - Earliest claimed: 2023-09-11 - Assignees: Microsoft Technology Licensing, LLC - Applicants: Microsoft Technology Licensing, LLC - Inventors: Terrence Huat Hin TAN; Charles Walter BOECKER; Ravi SHIVNARAINE; Edwin Magtoto GOZUN; Sokratis VAMVAKOS - Web page: https://patentgrep.com/patent/US20250085341A1 ## CPC - G01R 31/2896: {Testing of IC packages; Test features related to IC packages (containers per se H10W76/10, encapsulations per se H10W74/00)} - H10W 90/00: Package configurations - G01R 31/2884: {using dedicated test connectors, test elements or test circuits on the IC under test (G01R31/2855 takes precedence)} - G01R 31/318513: {Test of Multi-Chip-Moduls} - G01R 31/66: Testing of connections, e.g. of plugs or non-disconnectable joints (testing for incorrect line connections G01R31/55) - H10P 74/207: {Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics} - H10W 70/611: {for connecting multiple chips together} - H10W 70/685: comprising multiple insulating layers - H10W 72/00: Interconnections or connectors in packages - H10W 90/722: {between stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract Systems and methods for isolating faults in die-to-die interconnects are provided. A method includes providing a first transmission path, along a die-to-die interconnect, from a transmitter associated with a first die to an asynchronous buffer associated with a second die. The method further includes providing a second transmission path from voltage reference circuitry associated with the second die to the asynchronous buffer associated with the second die. The method further includes simultaneously enabling both the first transmission path and the second transmission path to allow the asynchronous buffer to receive inputs from both the transmitter associated with the first die and the voltage reference circuitry associated with the second die, such that the inputs received by the asynchronous buffer are indicative of: (1) no failure in the die-to-die interconnect, (2) an open failure in the die-to-die interconnect, or (3) a short failure in the die-to-die interconnect. ## Claims ### Claim 1 A system comprising: a first die coupled to a second die via a die-to-die interconnect; a first transmission path, along the die-to-die interconnect, from a transmitter associated with the first die to an asynchronous buffer associated with the second die; a second transmission path from voltage reference circuitry associated with the second die to the asynchronous buffer associated with the second die, wherein the voltage reference circuitry is configured to selectively output a first voltage or a second voltage, different from the first voltage; and control circuitry configured to simultaneously enable both the first transmission path and the second transmission path to allow the asynchronous buffer to receive inputs from both the transmitter associated with the first die and the voltage reference circuitry associated with the second die, wherein the inputs received by the asynchronous buffer are indicative of: (1) no failure in the die-to-die interconnect, (2) an open failure in the die-to-die interconnect, or (3) a short failure in the die-to-die interconnect. ### Claim 2 (depends on 1) The system of claim 1, wherein the inputs received by the asynchronous buffer are indicative of no failure in the die-to-die interconnect when the inputs correspond to the inputs received via the first transmission path. ### Claim 3 (depends on 1) The system of claim 1, wherein the inputs received by the asynchronous buffer are indicative of the open failure when the inputs correspond to the inputs received via the second transmission path. ### Claim 4 (depends on 1) The system of claim 1, wherein the asynchronous buffer is a single-ended unidirectional buffer. ### Claim 5 (depends on 1) The system of claim 1, wherein the asynchronous buffer has a threshold voltage amount equal to or less than half of a power supply voltage for the second die. ### Claim 6 (depends on 1) The system of claim 1, wherein the second die comprises a receiver, and wherein during fault isolation any inputs received at an input terminal associated with the second die are shorted with any inputs received from the voltage reference circuitry to an input terminal of the asynchronous buffer. ### Claim 7 (depends on 1) The system of claim 1, wherein the first voltage corresponds to a supply voltage associated with the second die, and wherein the second voltage corresponds to a ground voltage associated with the second die. ### Claim 8 (depends on 1) The system of claim 1, wherein the first transmission path has a lower impedance than the second transmission path. ### Claim 9 A method for isolating faults in an arrangement of dies comprising a first die coupled to a second die via a die-to-die interconnect, the method comprising: providing a first transmission path, along the die-to-die interconnect, from a transmitter associated with the first die to an asynchronous buffer associated with the second die; providing a second transmission path from voltage reference circuitry associated with the second die to the asynchronous buffer associated with the second die, wherein the voltage reference circuitry is configured to selectively output a first voltage or a second voltage, different from the first voltage; and simultaneously enabling both the first transmission path and the second transmission path to allow the asynchronous buffer to receive inputs from both the transmitter associated with the first die and the voltage reference circuitry associated with the second die, such that the inputs received by the asynchronous buffer are indicative of: (1) no failure in the die-to-die interconnect, (2) an open failure in the die-to-die interconnect, or (3) a short failure in the die-to-die interconnect. ### Claim 10 (depends on 9) The method of claim 9, wherein the asynchronous buffer is a single-ended unidirectional buffer. ### Claim 11 (depends on 9) The method of claim 9, wherein the asynchronous buffer has a threshold voltage amount equal to or less than half of a power supply voltage for the second die. ### Claim 12 (depends on 9) The method of claim 9, wherein the second die comprises a receiver, and wherein during fault isolation any inputs received at an input terminal associated with the second die are shorted with any inputs received from the voltage reference circuitry to an input terminal of the asynchronous buffer. ### Claim 13 (depends on 9) The method of claim 9, wherein the first voltage corresponds to a supply voltage associated with the second die, and wherein the second voltage corresponds to a ground voltage associated with the second die. ### Claim 14 (depends on 9) The method of claim 9, wherein the first transmission path has a lower impedance than the second transmission path. ### Claim 15 A system comprising: a first die coupled to a second die via a first die-to-die interconnect and a second die-to-die interconnect; a first transmission path, along the first die-to-die interconnect, from a first transmitter associated with the first die to a first asynchronous buffer associated with the first die; a second transmission path, along the second die-to-die interconnect, from a second transmitter associated with the second die to a second asynchronous buffer associated with the second die; a third transmission path from first voltage reference circuitry associated with the first die to the first asynchronous buffer associated with the first die and a fourth transmission path from second voltage reference circuitry associated with the second die to the second asynchronous buffer associated with the second die, wherein each of the first voltage reference circuitry and the second voltage reference circuitry is configured to selectively output a first voltage or a second voltage, different from the first voltage; and control circuitry configured to simultaneously enable the first transmission path, the second transmission path, the third transmission path, and the fourth transmission path in order to detect any neighbor short between the first die-to-die interconnect and the second die-to-die interconnect based on inputs received by the first asynchronous buffer and the second asynchronous buffer. ### Claim 16 (depends on 15) The system of claim 15, wherein each of the first asynchronous buffer and the second asynchronous buffer is a single-ended unidirectional buffer. ### Claim 17 (depends on 16) The system of claim 16, wherein each of the first asynchronous buffer and the second asynchronous buffer has a threshold voltage amount equal to or less than half of a power supply voltage for each of the first die and the second die. ### Claim 18 (depends on 15) The system of claim 15, wherein the first voltage corresponds to a supply voltage associated with each of the first die and the second die, and wherein the second voltage corresponds to a ground voltage associated with teach of the first die and the second die. ### Claim 19 (depends on 15) The system of claim 15, wherein the first transmission path has a lower impedance than the third transmission path, and wherein the second transmission path has a lower impedance than the fourth transmission path. ### Claim 20 (depends on 15) The system of claim 15, wherein the control circuitry is further configured to enable combinations of the first transmission path, the second transmission path, the third transmission path, and the fourth transmission path in order to detect: (1) no failure in the first die-to-die interconnect or the second die-to-die interconnect, (2) an open failure in the first die-to-die interconnect or the second die-to-die interconnect, or (3) a short failure in the first die-to-die interconnect or the second die-to-die interconnect based on inputs received by the first asynchronous buffer or the second asynchronous buffer.