# US 2025/0085339 A1 · Detecting circuit for detecting memory chip

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- Number: US 2025/0085339 A1
- Document ID: US20250085339A1
- Status: Published application
- Kind: A1
- Application number: 18/959,565
- Filed: 2024-11-25
- Published: 2025-03-13
- Earliest claimed: 2021-09-07
- Assignees: Nanya Technology Corporation
- Applicants: Nanya Technology Corporation
- Inventors: Yan-De LIN; Jui-Hsiu JAO
- Web page: https://patentgrep.com/patent/US20250085339A1

## CPC

- G01R 31/2893: {Handling, conveying or loading, e.g. belts, boats, vacuum fingers (G01R31/2867 takes precedence; handling semiconductor devices or wafers during manufacture or treatment H10P72/00)}
- G11C 29/006: {at wafer scale level, i.e. wafer scale integration [WSI]}
- G01R 31/2896: {Testing of IC packages; Test features related to IC packages (containers per se H10W76/10, encapsulations per se H10W74/00)}
- G01R 31/52: Testing for short-circuits, leakage current or ground faults
- G11C 11/401: forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C 2029/4402: {Internal storage of test result, quality data, chip identification, repair information}
- G11C 2029/5002: {Characteristic}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A method for detecting a memory chip includes the following steps coupling a detecting circuit to a first area and a second area of the memory chip, the second area is not overlapped with the first area; inputting a first detecting signal from the detecting circuit to the first area of the memory chip; burning out a cell of the detecting circuit; and inputting a second detecting signal from the detecting circuit to the second area of the memory chip.

## Claims

### Claim 1

A detecting circuit for detecting a memory chip, comprising:
an input pad, coupled to a first area of the memory chip, wherein the input pad is configured to input a first detecting signal to the first area of the memory chip; and
a cell, coupled to the input pad and a second area of the memory chip, wherein the second area is not overlapped with the first area;
wherein the cell is burned out such that the input pad inputs a second detecting signal to the second area of the memory chip.

### Claim 2 (depends on 1)

The detecting circuit of claim 1, wherein the detecting circuit comprises a switch, wherein the switch is turned on to be a resistance such that the second detecting signal is transmitted to the second area of the memory chip according a control signal.

### Claim 3 (depends on 1)

The detecting circuit of claim 1, wherein the memory chip comprises a 3D memory.

### Claim 4 (depends on 2)

The detecting circuit of claim 2, wherein the memory chip comprises word lines and bit lines, wherein the word lines are perpendicular to the bit lines.

### Claim 5 (depends on 4)

The detecting circuit of claim 4, wherein the word lines and the bit lines form a grid matrix in the memory chip, wherein the grid matrix comprises a first part and a second part, wherein the second part surrounds the first part.

### Claim 6 (depends on 5)

The detecting circuit of claim 5, wherein the first part and the second part are not overlapped with each other.

### Claim 7 (depends on 4)

The detecting circuit of claim 4, wherein the detecting circuit comprises a first detecting circuit and a second detecting circuit, wherein the first detecting circuit is coupled to the word lines, wherein the second detecting circuit is coupled to the bit lines.

### Claim 8 (depends on 1)

The detecting circuit of claim 1, wherein the detecting circuit further comprises detecting pads, wherein the detecting pads are configured to return detecting results of the first detecting signal and the second detecting signal back to the input pad.

### Claim 9

A detecting circuit for detecting a memory chip, wherein the memory chip comprises word lines and bit lines, the detecting circuit comprising:
a first detecting circuit coupled to the word lines for detecting the word lines, comprising:
a first input pad coupled to a first area of the memory chip and configured to input a first detecting signal to the first area of the memory chip; and
a first cell coupled to the first input pad and a second area of the memory chip, wherein the second area is not overlapped with the first area;
wherein the first cell is burned out such that the first input pad inputs a second detecting signal to the second area of the memory chip; and
a second detecting circuit coupled to the bit lines for detecting the bit lines, comprising:
a second input pad coupled to a third area of the memory chip and configured to input a third detecting signal to the third area of the memory chip; and
a second cell coupled to the second input pad and a fourth area of the memory chip, wherein the fourth area is not overlapped with the third area;
wherein the second cell is burned out such that the second input pad inputs a fourth detecting signal to the fourth area of the memory chip.

### Claim 10 (depends on 9)

The detecting circuit of claim 9, wherein the first detecting circuit comprises a first switch, wherein the first switch is turned on to be a first resistance such that the second detecting signal is transmitted to the second area of the memory chip according a first control signal.

### Claim 11 (depends on 10)

The detecting circuit of claim 10, wherein the second detecting circuit comprises a second switch, wherein the second switch is turned on to be a second resistance such that the fourth detecting signal is transmitted to the fourth area of the memory chip according a second control signal.

### Claim 12 (depends on 9)

The detecting circuit of claim 9, wherein the memory chip comprises a 3D memory.

### Claim 13 (depends on 9)

The detecting circuit of claim 9, wherein the word lines are perpendicular to the bit lines.

### Claim 14 (depends on 13)

The detecting circuit of claim 13, wherein the word lines and the bit lines form a grid matrix comprising a first grid and a plurality of second grids in the memory chip, wherein the second grids surround the first grid.

### Claim 15 (depends on 9)

The detecting circuit of claim 9, wherein the word lines and the bit lines of the memory chip are detected simultaneously.