Embedded chip-package, semiconductor package, method of forming an embedded chip-package, method of forming a semiconductor package, and method of analyzing an embedded chip-package or a semiconductor package
AssigneeInfineon Technologies AG
InventorsMahadi-Ul HASSAN, Mark PAVIER
Life of this patent
Estimating the term…
Abstract
An embedded chip-package is provided. In one example, the embedded chip-package includes a chip, an electrically insulating material at least partially encapsulating the chip, at least one metal layer configured to provide at least one electrically conductive connection to the chip, and an information section. The information section includes coded information about the embedded chip-package, wherein, in the information section, the information is coded as a pattern of electrically conductive portions and electrically insulating portions.
Claims18
An embedded chip-package, comprising:
- a chip;
- electrically insulating material at least partially encapsulating the chip;
- at least one metal layer configured to provide at least one electrically conductive connection to the chip;
- and
- an information section comprising coded information about the embedded chip-package;
- wherein, in the information section, the information is coded as a pattern of electrically conductive portions and electrically insulating portions.
An embedded chip-package, comprising:
- a chip;
- electrically insulating material at least partially encapsulating the chip;
- at least one metal layer configured to provide at least one electrically conductive connection to the chip;
- and
- at least one vertically elongated electrically conductive portion comprising a first end connected to the at least one metal layer and a second end arranged in the electrically insulating material,
- wherein the second end is electrically unconnected.
Dependencies are inferred from the claim text.