US 2025/0076918 A1 · CLOCK SYNCHRONIZATION PULSE WIDTH SCALING

Abstract

An electronic circuit includes an oscillator circuit, a first divider circuit, a synchronization control circuit, and a peripheral circuit. The oscillator circuit is configured to generate a base frequency clock. The first divider circuit is configured to divide the base frequency clock by a first selectable divisor to generate a divided clock. The synchronization control circuit is configured to generate a synchronization pulse that controls a change of the first selectable divisor in the first divider circuit from a first value to a second value. A pulse width of the synchronization pulse is based on the first value of the first selectable divisor. The peripheral circuit is coupled to the first divider circuit and the synchronization control circuit. The peripheral circuit includes a second divider circuit. The second divider circuit divides the divided clock by a second selectable divisor, and change the second selectable divisor responsive to the synchronization pulse.

Claims20

Dependent claims

A system, comprising:

a first circuit configured to:
receive a clock signal;
divide the clock signal based on a value of a first divisor to generate a first clock signal;
a second circuit configured to:
receive the first clock signal;
and
divide the first clock based on a value of a second divisor to generate a second clock signal;
and
a third circuit configured to:
generate a pulse to cause the first circuit and the second circuit to concurrently change the value of the first divisor and the value of the second divisor.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application

18/951,807Filed 19 Nov 2024

Priority

27 Dec 2021

Published

6 Mar 2025

Term ends

Not estimatedThe source records don’t support an estimate.

Classification6 codes

G06F 1/12
Generating or distributing clock signals or signals derived directly therefrom: synchronisation of different clock signals provided by a plurality…
G06F 1/08
Generating or distributing clock signals or signals derived directly therefrom: clock generators with changeable or programmable clock frequency
G06F 1/10
Generating or distributing clock signals or signals derived directly therefrom: distribution of clock signals , e.g. skew
H03K 21/023
Input circuits: comprising pulse shaping or differentiating circuits

Clock synchronization pulse width scaling

Life of this patent

Clock synchronization pulse width scaling

Life of this patent

Abstract

Claims20