Transmitter and transceiver with switching jitter improvement

A transmitter comprising:

• an encoder configured to encode an input signal representable by x levels, where x is a natural number of 3 or more, and output a plurality of encoded signals representing a multi-bit binary number including a most significant bit, a middle bit, and a least significant bit;
• an edge adjustment circuit configured to generate a plurality of adjusted encoded signals by adjusting a falling edge timing of a first one of the encoded signals corresponding to the most significant bit and a rising edge timing of a second one of the encoded signals corresponding to the least significant bit by a first adjustment timing value, and adjusting edge timing of a third one of the encoded signals corresponding to the middle bit by a second adjustment timing value different from the first adjustment timing value;
• and
• a driver circuit configured to generate and output an output signal having the x levels based on the plurality of adjusted encoded signals.