Signal receiving apparatus, clock and data recovery circuit and clock and data recovery method thereof

A clock and data recovery method, comprising:

• performing a burst mode over-sampling on an input analog data signal by a sampling circuit according to a sampling timing in a burst mode to generate a plurality of over-sampling results;
• determining neighboring two of the over-sampling results having opposite logic states in the burst mode by a selection circuit to accordingly select a plurality of data edge sampling results and a plurality of data center sampling results interlaced with each other and having a same time period with the input analog data signal from the over-sampling results to output a plurality of output sampling results;
• performing phase detection according to the output sampling results by a phase detection circuit to generate a phase locking direction;
• and
• adjusting the sampling timing of the sampling circuit according to the phase locking direction by a phase adjusting circuit to track the input analog data signal.

A signal receiving apparatus, comprising:

• an equalizer circuit configured to receive an external signal perform equalization thereon to generate an input analog data signal;
• a clock and data recovery circuit comprising:
• a sampling circuit configured to perform a burst mode over-sampling on the input analog data signal according to a sampling timing in a burst mode to generate a plurality of over-sampling results;
• a selection circuit configured to determine neighboring two of the over-sampling results having opposite logic states in the burst mode to accordingly select a plurality of data edge sampling results and a plurality of data center sampling results interlaced with each other and having a same time period with the input analog data signal from the over-sampling results to output a plurality of output sampling results;
• a phase detection circuit configured to perform phase detection according to the output sampling results to generate a phase locking direction;
• and
• a phase adjusting circuit configured to adjust the sampling timing of the sampling circuit according to the phase locking direction to track the input analog data signal;
• and
• a digital processing circuit configured to receive and process an output digital data signal from the selection circuit.