Superconductive integrated circuit devices with on-chip testing

A non-transitory computer readable medium comprising stored instructions, which when executed by a processor, cause the processor to:

• receive a superconductive circuit design comprising superconductive logic elements;
• determine a first testability characteristic for first test circuitry at a first node within the superconductive circuit design, wherein the first testability characteristic corresponds to one or more of a test generation control level and a test observability control level;
• and
• generate an updated superconductive circuit design from the superconductive circuit design based on the first testability characteristic of the first test circuitry, wherein the superconductive circuit design includes the first test circuitry at the first node.