Memory and Method for Manufacturing Thereof

A method for manufacturing the memory, wherein the memory has a memory array region and a logic region, and the method comprises:

• providing a bottom circuit layer and a silicon oxide dielectric layer arranged in a stacked manner;
• forming bottom electrodes penetrating the silicon oxide dielectric layer in the memory array region and extending to the bottom circuit layer, and forming a first portion of top contact body penetrating the silicon oxide dielectric layer in the logic region and extending to the bottom circuit layer;
• forming a memory cell layer covering the bottom electrodes;
• forming a patterned dielectric layer over the bottom circuit layer, wherein the patterned dielectric layer has first vias and second vias, the first vias exposes the memory cell layer and the second vias expose the first portion of top contact body;
• forming hard masks filling the first vias, and forming a second portion of top contact body filling the second vias;
• and
• etching the memory cell layer to form memory cells according to the hard masks.

A memory, having a memory array region and a logic region, and comprising:

• a bottom circuit layer and a silicon oxide dielectric layer arranged in a stacked manner;
• bottom electrodes penetrating the silicon oxide dielectric layer in the array region and extending to the bottom circuit layer;
• a first portion of top contact body penetrating the silicon oxide dielectric layer in the logic region and extending to the bottom circuit layer;
• memory cell layers covering the bottom electrodes one by one;
• hard masks located one by one on a side of the memory cells facing away from the bottom circuit layer, wherein projections of the hard masks over the bottom circuit layer coincides with projections of the memory cells on the bottom circuit layer;
• and
• a second portion of top contact body located on a side of the first portion of top contact body facing away from the bottom circuit layer, wherein a projection of the second portion of top contact body over the bottom circuit layer is located in a projection of the first portion of top contact body on the bottom circuit layer.