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AssigneepSemi Corporation
InventorsJagar Singh, Kazuhiko Shibata, Simon Edward Willard
Estimating the term…
Structures and methods for better optimizing the performance of all the circuitry of an SOI IC. Embodiments include SOI IC having dual-thickness active areas, such that digital and non-RF analog circuitry may be fabricated on a relatively thin active layer while RF circuitry may be fabricated on a relatively thick active layer. Fabrication of RF circuitry on the relatively thick active layer allows for improvements to the RON*COFF figure of merit for the FET devices, and for optimizations not feasible for RF circuitry fabricated on a relatively thin active layer. Structures and methods for two-level shallow-trench isolation (STI) structures and electrical contacts are disclosed. Some embodiments may include a substrate contact extending from the substantially planar upper surface of a dielectric layer overlaying the thin and thick active areas to at least the BOX layer.
An integrated circuit substructure having dual-thickness active areas, including:
A substructure of a silicon-on insulator integrated circuit having dual-thickness active areas, including:
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Dependencies are inferred from the claim text.