Semiconductor devices and methods of fabricating the same

A semiconductor device, comprising:

• a first active pattern extending in a first direction across an underlying substrate;
• a gate structure extending in a second direction intersecting the first direction, on the first active pattern;
• a first source/drain contact electrically connected to a first source/drain region of the first active pattern, on one side of the gate structure;
• a first via pattern electrically connected to an upper surface of the first source/drain contact;
• a rail pattern extending in the first direction, and electrically connected to a side surface of the first pattern;
• and
• a wiring pattern extending in the first direction, and electrically connected to an upper surface of the rail pattern;
• and
• wherein the first source/drain contact includes a first recess, which is recessed more downwardly than the upper surface of the first source/drain contact.

A semiconductor device, comprising:

• a first active pattern extending in a first direction across an underlying substrate;
• a gate structure extending in a second direction intersecting the first direction, on the first active pattern;
• a first source/drain region in the first active pattern, on both sides of the gate structure;
• a first interlayer insulating film covering the gate structure and the first source/drain region, on the substrate;
• a first source/drain contact that penetrates through the first interlayer insulating film on one side of the gate structure, and is electrically connected to the first source/drain region;
• a second source/drain contact that penetrates through the first interlayer insulating film on the other side of the gate structure, and is electrically connected to the first source/drain region;
• an etch stop layer covering an upper surface of the first interlayer insulating film, an upper surface of the first source/drain contact, and an upper surface of the second source/drain contact;
• a second interlayer insulating film on the etch stop layer;
• a first via pattern that penetrates through the etch stop layer and the second interlayer insulating film, and is electrically connected to the upper surface of the first source/drain contact;
• a second via pattern that penetrates through the etch stop layer and the second interlayer insulating film, and is electrically connected to the upper surface of the second source/drain contact;
• a first rail pattern extending in the first direction on the etch stop layer;
• and
• a first power wiring that extends in the first direction on the second interlayer insulating film, and is electrically connected to an upper surface of the first rail pattern;
• wherein the first via pattern is spaced apart from the first rail pattern in the second direction;
• wherein the second via pattern is connected to a side surface of the first rail pattern;
• wherein the first source/drain contact includes a first recess, which is recessed more downwardly than the upper surface of the first source/drain contact;
• and
• wherein the second source/drain contact includes a second recess, which is recessed more downwardly than the upper surface of the second source/drain contact.