Isolation module for backside power delivery

A method of forming a portion of a gate-all-around field-effect transistor (GAA FET), comprising:

• performing a selective deposition process to form selective cap layers at bottoms of contact trenches within portions of a substrate isolated by shallow trench isolations (STIs), wherein the contact trenches each interface with an S/D epitaxial (epi) layer with an extension region;
• performing a substrate angled etch process to etch sidewalls of the contact trenches, enlarging top critical dimension (CD) of the contact trenches;
• performing a substrate selective removal plasma (SRP) etch process to isotropically etch the substrate within the contact trenches;
• performing a recess fill process to fill the contact trenches with dielectric layers;
• performing an inter-layer dielectric (ILD) recess process to partially remove the substrate between the dielectric layers within the contact trenches and form an ILD recess;
• performing a substrate isotropic etch process to partially remove the substrate within the ILD recess;
• performing an ILD formation process to form an ILD within the ILD recess;
• and
• performing a contact recess process to partially remove the dielectric layer within the contact trenches;
• performing a contact liner formation process to form an interface at the bottoms of the contact trenches and a contact liner on exposed inner surfaces of the contact trenches;
• performing a contact metallization process to fill the contact trenches with metal fill material;
• and
• performing a contact metal chemical mechanical polishing (CMP) process to remove the over-filled metal fill material and form a metal contact.

A semiconductor structure forming a portion of a gate-all-around field-effect transistor (GAA FET), comprising:

• channel layers embedded in an inter-layer dielectric (ILD) formed on a substrate, the channel layers extending in a first direction;
• a metal gate embedded in the ILD, the metal gate extending in the first direction;
• a source/drain (S/D) epitaxial (epi) layer that electrically connects the channel layers a S/D contact via an extension region and S/D epitaxial layers on both sides of the channel layers;
• shallow trench isolations (STIs) formed within the substrate;
• a metal contact and a dielectric layer formed between the STIs, the metal contact and the dielectric layer extending in a second direction orthogonal to the first direction, wherein the metal contact is electrically connected to the S/D epi layer via the extension region;
• and
• extension protect layers formed at bottom corners of the ILD interfacing the dielectric layers with the extension region.