Semiconductor device and manufacturing method thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChun Hsiung TSAI, Chih-Hsin KO, Clement Hsing Jen WANN, Ya-Yun CHENG
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Abstract
A semiconductor device including a FET includes an isolation insulating layer disposed in a trench of the substrate, a gate dielectric layer disposed over a channel region of the substrate, a gate electrode disposed over the gate dielectric layer, a source and a drain disposed adjacent to the channel region, and an embedded insulating layer disposed below the source, the drain and the gate electrode and both ends of the embedded insulating layer are connected to the isolation insulating layer.
Claims20
A semiconductor device, comprising:
- a gate structure disposed over channel region in a substrate;
- source/drain regions disposed in the substrate adjacent to the channel region;
- an isolation insulating layer disposed in the substrate adjacent to the source/drain regions;
- an embedded insulating layer disposed in the substrate below the channel region;
- and
- a void disposed in the embedded insulating layer.
A semiconductor device, comprising:
- a gate structure disposed over channel region in a substrate;
- source and drain regions disposed in the substrate adjacent to the channel region;
- a first isolation insulating layer disposed in the substrate adjacent to an outside edge of the source region along a first direction parallel to a main surface of the substrate in cross section;
- a second isolation insulating layer disposed in the substrate adjacent to an outside edge of the drain region along the first direction in cross section;
- a first embedded insulating layer protruding from the first isolation insulating layer disposed in the substrate below the source region;
- a second embedded insulating layer protruding from the second isolation insulating layer in the substrate below the drain region;
- a first void disposed in the first embedded insulating layer;
- and
- a second void disposed in the second embedded insulating layer.
A semiconductor device, comprising:
- a gate structure disposed over channel region in a substrate;
- source and drain regions disposed in a first main surface of the substrate adjacent to the channel region;
- a first isolation insulating layer disposed in the substrate adjacent to an outside edge of the source region along a first direction parallel to a main surface of the substrate in cross section;
- a second isolation insulating layer disposed in the substrate adjacent to an outside edge of the drain region along the first direction in cross section;
- an embedded insulating layer disposed in the substrate extending from the first isolation insulating layer to the second isolation insulating layer below the channel region,
- wherein the embedded insulating layer is connected to the first isolation insulating layer and the second isolation insulating layer, and
- the embedded insulating layer is spaced apart from a second main surface of the substrate opposing the first main surface;
- and
- a void disposed in the embedded insulating layer below the channel region.
Dependencies are inferred from the claim text.