Sic trench devices having n-type gate oxide shield zones

A SiC shielded gate trench (SGT) device comprising a plurality of unit cells with each unit cell in an active area comprising:

• an epitaxial layer of a first conductivity type on a substrate;
• at least one gate trench surrounded by a source region of said first conductivity type encompassed in a body region of a second conductivity type;
• said gate trench being filled with a gate electrode and a shielded gate electrode;
• said shielded gate electrode being insulated from said epitaxial layer by a first insulating film, said gate electrode being insulated from said epitaxial layer by a gate oxide, said shielded gate electrode and said gate electrode being insulated from each other by an (Inter-polysilicon Oxide) IPO film, said gate oxide surrounding said gate electrode and having a less thickness than a thickness of said first insulating film;
• at least one N-shield zone of said first conductivity type for gate oxide protection disposed at a position deeper than said shielded gate electrode in said epitaxial layer with a doping concentration higher than a doping concentration of said epitaxial layer;
• a P-shield zone of said second conductivity type for gate oxide electric-filed reduction adjoining a lower surface of said body region and being apart from said gate trench;
• and
• said body region and said source region being shorted to a source metal through source contacts.

A SiC SGT device comprising a plurality of unit cells with each unit cell in an active area comprising:

• an epitaxial layer of a first conductivity type on a substrate of said first conductivity type;
• at least two gate trenches surrounded by a source region of said first conductivity type encompassed in a body region of a second conductivity type;
• said gate trenches being filled with a gate electrode and a shielded gate electrode;
• said shielded gate electrode being insulated from said epitaxial layer by a first insulating film, said gate electrode being insulated from said epitaxial layer by a gate oxide, said shielded gate electrode and said gate electrode being insulated from each other by an (inter-polysilicon oxide) IPO film, said gate oxide surrounding said gate electrode and having a less thickness than a thickness of said first insulating film;
• at least one N-shield zone of said first conductivity type for gate oxide protection disposed at a position deeper than said shielded gate electrode in said epitaxial layer with a doping concentration higher than a doping concentration of said epitaxial layer;
• a P-shield zone of said second conductivity type for gate oxide electric-filed reduction adjoining lower surface of said body region and being apart from said gate trench;
• and
• said epitaxial layer further an oxide charge balance (OCB) region and a buffer region;
• said OCB region of said first conductivity type formed in a mesa area between two adjacent said gate trenches below said body region and above a bottom of said shielded gate electrode;
• said buffer region of said first conductivity in said epitaxial layer formed between said substrate and said OCB region;
• and
• said epitaxial layer in said OCB region has MSE layers with different doping concentrations decreasing stepwise in a direction from a bottom of said shielded gate electrode to said body region along sidewalls of said gate trench, wherein each of said MSE layers has a uniform doping concentration as grown.