A memory device

A method for producing a memory device, the method comprising

• depositing semiconductor layers on a substrate (90), the semiconductor layers being stacked in a stacking direction, whereby a semiconductor structure is formed out of the deposited semiconductor layers;
• etching the semiconductor structure to form a pillar, the pillar having an axial direction in the stacking direction;
• forming a transistor in the pillar, the transistor comprising a source, a body, and a drain, wherein the source, body, and drain are respective pillar segments along the axial direction of the pillar, wherein a source pillar segment and a drain pillar segment are separated by a body pillar segment, wherein the transistor is either
• an NPN transistor, wherein the source pillar segment is n-doped, the body pillar segment is p-doped, and the drain pillar segment is n-doped;
• or
• a PNP transistor, wherein the source pillar segment is p-doped, the body pillar segment is n-doped, and the drain pillar segment is p-doped;
• wherein at least one p-doped pillar segment of the transistor comprises a plurality of semiconductor layers, of the deposited semiconductor layers, stacked in the axial direction of the pillar, wherein layers of the plurality of semiconductor layers of the p-doped pillar segment are made of AlGaN or GaN, and wherein the plurality of semiconductor layers of the p-doped pillar segment is configured such that an aluminum content changes between each consecutive layer such that every second layer has a lower aluminum content than the neighboring mutually opposite layers thereof;
• forming a charge trap configured to store a charge and to control a threshold voltage of the transistor by said stored charge;
• wherein the transistor and the charge trap are parts of a memory cell of the memory device.