Semiconductor device and electronic system including the same

A semiconductor device, comprising:

• a source structure that includes a first source layer, a second source layer on the first source layer, and a third source layer on the second source layer;
• a gate stack structure on the source structure, the gate stack structure including dielectric patterns and conductive patterns that are alternately stacked;
• and
• a memory channel structure penetrating the gate stack structure,
• wherein the memory channel structure includes:
• a channel layer;
• a tunnel dielectric layer surrounding the channel layer;
• a data storage layer surrounding the tunnel dielectric layer;
• and
• a blocking layer surrounding the data storage layer,
• wherein the blocking layer is spaced apart from an upper surface of the second source layer,
• wherein the second source layer includes a surface directly contacting the tunnel dielectric layer and the data storage layer, and
• wherein the third source layer includes a first top surface directly contacting the blocking layer.

An electronic system, comprising:

• a main board;
• a semiconductor device on the main board;
• and
• a controller on the main board, the controller is electrically connected to the semiconductor device,
• wherein the semiconductor device includes:
• a source structure including a first source layer, a second source layer on the first source layer, and a third source layer on the second source layer;
• a gate stack structure on the source structure, the gate stack structure including dielectric patterns and conductive patterns that are alternately stacked;
• and
• a memory channel structure penetrating the gate stack structure,
• wherein a lowermost dielectric pattern of the dielectric patterns is a lower dielectric pattern, wherein the lower dielectric pattern directly contacts the third source layer,
• wherein the memory channel structure includes:
• a dielectric capping layer;
• a channel layer surrounding the dielectric capping layer;
• a tunnel dielectric layer surrounding the channel layer;
• a data storage layer surrounding the tunnel dielectric layer;
• and
• a blocking layer surrounding the data storage layer,
• wherein the second source layer includes a surface directly contacting the tunnel dielectric layer and the channel layer,
• wherein the third source layer includes a top surface directly contacting the blocking layer, and
• wherein a width of the surface of the second source layer is greater than a width of the top surface of the third source layer.