NAND String Utilizing Floating Body Memory Cell

A semiconductor memory array comprising:

• a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell includes:
• a floating body region configured to be charged to a level indicative of a state of the semiconductor memory cell, said floating body region have a first conductivity type selected from p-type conductivity type and n-type conductivity type;
• a first region in electrical contact with said floating body region having a second conductivity type different from said first conductivity type;
• a second region in electrical contact with said floating body region, spaced apart from said first region and having said second conductivity type;
• a third region in electrical contact with said floating body region, spaced apart from said first and second regions and having said second conductivity type;
• wherein said third region is configured to function as a collector region to maintain a charge of said floating body region, thereby maintaining said state of said semiconductor memory cell;
• and
• a gate positioned between said first and second regions;
• wherein said gate surrounds a portion of said floating body region;
• wherein a doping concentration of said portion of said floating body region surrounded by said gate is different from a doping concentration of a part of said floating body region not surrounded by said gate;
• and
• wherein said third region is commonly connected to at least two of said semiconductor memory cells.

An integrated circuit comprising:

• an array of memory cells, the array comprising a plurality of semiconductor memory cells arranged in a plurality of rows and a plurality of columns, each said semiconductor memory cell comprising:
• a floating body region configured to be charged to a level indicative of a state of the semiconductor memory cell, said floating body region have a first conductivity type selected from p-type conductivity type and n-type conductivity type;
• a first region in electrical contact with said floating body region having a second conductivity type different from said first conductivity type;
• a second region in electrical contact with said floating body region, spaced apart from said first region and having said second conductivity type;
• a third region in electrical contact with said floating body region, spaced apart from said first and second regions and having said second conductivity type;
• wherein said third region is configured to function as a collector region to maintain a charge of said floating body region, thereby maintaining said state of said semiconductor memory cell;
• a gate positioned between said first and second regions;
• wherein said gate surround a portion of said floating body region;
• wherein a doping concentration of said portion of said floating body region surrounded by said gate is different from a doping concentration of a part of said floating body region not surrounded by said gate;
• wherein said third region is commonly connected to at least two of said semiconductor memory cells;
• and
• a control circuit configured to provide electrical signals to said third region.