Memory cell with buried power grid, and method of fabricating same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHidehiro FUJIWARA, Chih-Yu LIN, Yen-Huei CHEN, Wei-Chang ZHAO, Yi-Hsin NIEN
Life of this patent
Estimating the term…
Loading patent…
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHidehiro FUJIWARA, Chih-Yu LIN, Yen-Huei CHEN, Wei-Chang ZHAO, Yi-Hsin NIEN
Estimating the term…
A method (of manufacturing a memory device) includes forming active regions extending in a first direction; over the active regions, doing as follows including, forming gate structures extending in a second direction perpendicular to the first direction, and forming contact-to-source/drain structures (MD structures) which extend in the second direction and are interspersed among corresponding ones of the gate structures; forming via-to-gate/MD (VGD) structures over corresponding ones of the gate structures and the MD structures; in a first metallization layer over the VGD structures, forming first front-side segments extending in the first direction and including one or more front-side routing (FRTE) segments; under the active regions, forming buried segment-to-source/drain structures (BVD structures); and in a first buried metallization layer under the BVD structures, forming first back-side segments extending in the first direction and including one or more first back-side power grid (BPG) segments.
A method of manufacturing a device, the method comprising:
A device comprising:
A device comprising:
Dependencies are inferred from the claim text.