Low Noise, Supply Rejecting Linear Phase Interpolator

A phase interpolator circuit, comprising:

• a capacitance circuit;
• a switched resistor network, which has a configurable resistance and is configured to:
• receive a start-phase reference signal;
• receive an end-phase reference signal that is delayed relative to the start-phase reference signal;
• and
• generate an interpolated output signal corresponding to a voltage on the capacitance circuit;
• and
• interpolation management circuitry, configured to:
• receive an interpolation code that defines an intermediate phase between the start-phase reference signal and the end-phase reference signal;
• charge or discharge the capacitance circuit through the switched resistor network;
• control the switched resistor network to set a phase of the interpolated output signal to match the intermediate phase defined by the interpolation code,
• wherein the interpolation management circuitry is further configured to:
• (i) responsively to a transition in the start-phase reference signal, set the resistance of the switched resistor network based on the interpolation code;
• and,
• (ii) responsively to a voltage level on the capacitance circuit, set the resistance of the switched resistor network to a constant resistance that is independent of the interpolation code, and flow through the capacitance circuit an additional boosting current that accelerates charging or discharging of the capacitance circuit.