Semiconductor package

A semiconductor package comprising:

• a first redistribution substrate;
• a connection substrate on the first redistribution substrate, the connection substrate having an opening in the connection substrate;
• a first logic chip on the first redistribution substrate and in the opening of the connection substrate;
• a first molding layer that covers the connection substrate and the first logic chip;
• a dielectric pattern on the first molding layer;
• and
• a second logic chip on the dielectric pattern,
• wherein the first molding layer extends into a gap between the connection substrate and the first logic chip and includes a resin material containing a filler.

A semiconductor package comprising:

• a first redistribution substrate that includes a redistribution line and a redistribution via;
• a connection substrate on the first redistribution substrate, the connection substrate having an opening that includes a connection via;
• a first logic chip in the opening in the connection substrate, the first logic chip including a through via;
• and
• a second logic chip on the first logic chip,
• wherein a width of the redistribution via decreases with an increasing distance from a bottom surface of the first redistribution substrate,
• wherein a width of the connection via increases with the increasing distance from the bottom surface of the first redistribution substrate, and
• wherein a size in a first direction of the first logic chip is less than a size in the first direction of the second logic chip.