US 2025/0062297 A1Published application

Semiconductor package

AssigneeSamsung Electronics Co., Ltd.

InventorsJinwon CHAE, Taehong MIN, Daehan SONG, Inwook JUNG

Life of this patent

Estimating the term…

Loading patent…

Abstract

A semiconductor package may comprise an interposer substrate including a substrate and a lower protective layer, a through-via passing through the substrate and the lower protective layer, a lower pad on the lower protective layer and in contact with the through-via, an interlayer insulating layer on an upper surface of the substrate, and an interconnection structure in the interlayer insulating layer, a plurality of first semiconductor chips on an upper surface of the interposer substrate and electrically connected to the interconnection structure, a second semiconductor chip on the upper surface of the interposer substrate apart from the plurality of first semiconductor chips and electrically connected to the interconnection structure, an encapsulant covering at least a portion of the plurality of first semiconductor chips and the second semiconductor chip and connection conductors on the lower surface of the lower protective layer and electrically connected to the lower pad.

Claims20

Dependent claims

A semiconductor package, comprising:

an interposer substrate including a substrate, a lower protective layer on a lower surface of the substrate, a through-via passing through the substrate and the lower protective layer, a lower pad on a lower surface of the lower protective layer, the lower pad in contact with the through-via, an interlayer insulating layer on an upper surface of the substrate, and an interconnection structure in the interlayer insulating layer;
a plurality of first semiconductor chips on an upper surface of the interposer substrate, the plurality of first semiconductor chips electrically connected to the interconnection structure and stacked in a direction perpendicular to the upper surface of the interposer substrate;
a second semiconductor chip on the upper surface of the interposer substrate and apart from the plurality of first semiconductor chips, the second semiconductor chip electrically connected to the interconnection structure;
an encapsulant on the upper surface of the interposer substrate, the encapsulant covering at least a portion of the plurality of first semiconductor chips and at least a portion of the second semiconductor chip, respectively;
and
connection conductors on the lower surface of the lower protective layer, the connection conductors electrically connected to the lower pad,
wherein the plurality of first semiconductor chips includes
a lowermost semiconductor chip at a lowest level and
upper semiconductor chips stacked on the lowermost semiconductor chip,
a thickness of the lowermost semiconductor chip is greater than or equal to a thickness of one of the upper semiconductor chips, and
a width of the lowermost semiconductor chip is same as a width of the upper semiconductor chips.

8 more elements

Dependencies are inferred from the claim text.