Package and manufacturing method thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsMing-Fa Chen, Sung-Feng Yeh, Jian-Wei Hong
Life of this patent
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Abstract
A package includes a first die, a second die, a first encapsulant, first through insulating vias (TIV), second encapsulant, and second TIVs. The second die is stacked on the first die. The first encapsulant laterally encapsulates the first die. The first TIVs are aside the first die. The first TIVs penetrate through the first encapsulant and are electrically floating. The second encapsulant laterally encapsulates the second die. The second TIVs are aside the second die. The second TIVs penetrate through the second encapsulant and are electrically floating. The second TIVs are substantially aligned with the first TIVs.
Claims20
A package, comprising:
- a first die;
- a second die stacked on the first die;
- a first encapsulant laterally encapsulating the first die;
- first through insulating vias (TIV) aside the first die, wherein the first TIVs penetrate through the first encapsulant and are electrically floating;
- a second encapsulant laterally encapsulating the second die;
- and
- second TIVs aside the second die, wherein the second TIVs penetrate through the second encapsulant and are electrically floating, and the second TIVs are substantially aligned with the first TIVs.
A manufacturing method of a package, comprising:
- embedding contact vias in a semiconductor carrier, wherein the semiconductor carrier exposes top surfaces of the contact vias, and the contact vias are electrically grounded;
- forming alignment marks physically contacting the top surfaces of the contact vias;
- placing a first die over the semiconductor carrier;
- laterally encapsulating the first die by a first encapsulant;
- forming first through insulating vias (TIV) in the first encapsulant, wherein the first TIVs are in physical contact with the alignment marks so that the first TIVs are electrically grounded through the alignment marks and the contact vias;
- grinding the first die, the first encapsulant, and the first TIVs;
- and
- stacking a second die over the first die.
A manufacturing method of a package, comprising:
- providing a semiconductor carrier having die regions and scribe line regions located between two adjacent die regions;
- embedding contact vias in the scribe line regions of the semiconductor carrier, wherein the semiconductor carrier exposes top surfaces of the contact vias, and the contact vias are electrically grounded;
- forming alignment marks physically contacting the top surfaces of the contact vias, wherein the alignment marks are located in the scribe line regions;
- placing first dies over the semiconductor carrier in the die regions;
- encapsulating the first dies by a first encapsulant;
- forming through insulating vias (TIV) in the scribe line regions, wherein the TIVs are in physical contact with the alignment marks so that the TIVs are electrically grounded through the alignment marks and the contact vias;
- grinding the first dies, the first encapsulant, and the TIVs;
- stacking a second die over the first die;
- and
- performing a singulation process to remove the contact vias, the alignment marks, and the TIVs located in the scribe line regions.
Dependencies are inferred from the claim text.