Semiconductor package
AssigneeSK hynix Inc.
InventorSeong Ju LEE
Life of this patent
Estimating the term…
Abstract
A semiconductor package includes a substrate; a first chip and a second chip stacked on the substrate, each including a first pad, a cell region, a first level serializer-deserializer connected to the first pad, a second level serializer-deserializer connected between the first level serializer-deserializer and the cell region and a second pad that is connected to a node between the first level serializer-deserializer and the second level serializer-deserializer; and a first connection member connecting the second pad of the first chip to the second pad of the second chip.
Claims50
A semiconductor package comprising:
- a substrate;
- a first chip and a second chip stacked on the substrate, each including a first pad, a cell region, a first level serializer-deserializer connected to the first pad, a second level serializer-deserializer connected between the first level serializer-deserializer and the cell region, and a second pad that is connected to a node between the first level serializer-deserializer and the second level serializer-deserializer;
- and
- a first connection member connecting the second pad of the first chip to the second pad of the second chip.
A semiconductor package comprising:
- a first chip disposed on a substrate, the first chip including an external data pad, a first slice data pad, and a first level serializer-deserializer connected between the external data pad and the first slice data pad;
- a second chip stacked on the first chip, the second chip including a second slice data pad and a second level serializer-deserializer connected to the second slice data pad;
- and
- a first connection member connecting the first slice data pad and the second slice data pad.
A semiconductor package comprising:
- a substrate;
- first and second chips stacked on the substrate, each including an external signal pad that is included in a first pad column located in a first edge portion and a slice signal pad that is included in a second pad column located in the first edge portion;
- a first connection member connecting the slice signal pad of the first chip to the slice signal pad of the second chip;
- and
- a second connection member connecting the substrate to the external signal pad of the first chip,
- wherein, in each of the first and second chips, the first pad column is disposed between a chip side surface included in the first edge portion and the second pad column.
A semiconductor package comprising:
- a substrate;
- a first chip stacked on the substrate, the first chip including an external signal pad that is included in a first pad column located in a first edge portion and a first slice signal pad that is included in a second pad column located in the first edge portion;
- a second chip stacked on the first chip, the second chip including a second slice signal pad;
- a first connection member connecting the first slice signal pad to the second slice signal pad;
- and
- a second connection member connecting the substrate to the external signal pad,
- wherein the first pad column is disposed between a side surface of the first chip included in the first edge portion and the second pad column.
Dependencies are inferred from the claim text.