Power overlay structure for a multi-chip semiconductor package

A multi-chip semiconductor package comprising:

• an interconnect layer having an upper surface and a bottom surface, wherein said interconnect layer comprises a dielectric material,
• at least one common source pad disposed on said upper surface of said interconnect layer;
• at least one common gate pad disposed on said upper surface of said interconnect layer;
• and
• a plurality of semiconductor devices each comprising a gate pad and at least one source pad adhered onto said interconnect layer;
• wherein said source pads of said plurality of semiconductor devices are electrically connected to said at least one common source pad, and wherein said source pads of said plurality of semiconductor devices are electrically connected in parallel with one another;
• and
• wherein said gate pads of said plurality of semiconductor devices are electrically connected to said common gate pad, and wherein said gate pads of said plurality of semiconductor devices are electrically connected in parallel with one another.