Package architectures having vertically stacked dies with solder interconnects

A microelectronic assembly, comprising:

• a first integrated circuit (IC) die having a first surface, a second surface opposite the first surface, and a third surface orthogonal to the first and second surfaces, the first IC die including conductive traces that are parallel to the first and second surfaces and the conductive traces are exposed at the third surface;
• a second IC die including a fourth surface and a fifth surface opposite the fourth surface, wherein the fourth surface of the second IC die is electrically coupled to the third surface of the first IC die by first interconnects including solder;
• and
• a package substrate electrically coupled to the fifth surface of the second IC die by second interconnects.